Showing posts with label eSilicon. Show all posts
Showing posts with label eSilicon. Show all posts

Thursday, May 9, 2019

eSilicon tapes out 7nm Combo PHY for high bandwidth memory

eSilicon announced the tapeout of a 7nm test chip to provide silicon validation of its physical interface (PHY) to support the new JEDEC standard JESD235B, referred to informally as high bandwidth memory (HBM) 2E and emerging low-latency HBM technology. 

The chip contains a 7nm PHY from eSilicon and a controller from Northwest Logic.  This 7nm test chip, along with a previously taped out 7nm test chip will be part of a 2.5D test system to verify end-to-end support for the new HBM interfaces. The PHY design is a “combo” device that supports HBM2, HBM2E and the emerging low-latency HBM interface in one physical IP block.

When compared to HBM2, the HBM2E standard increases total capacity from 8GB to 16GB, bandwidth per pin from 2.4 Gb/s to 3.2 Gb/s and bandwidth per stack from 307.2 GB/s to 410 GB/s. Samsung Electronics announced the industry’s first HBM2E to deliver the 3.2 Gb/s per-pin transfer speed, at NVIDIA’s GPU Technology Conference in March.

“HBM memory stacks are a critical component for many of our new FinFET-class 2.5D ASICs,” said Hugh Durdan, vice president, strategy and products at eSilicon. “We look forward to validating the performance and functionality of our combo PHY and Northwest Logic’s controller to support the latest HBM capabilities.”

http://www.esilicon.com

Wednesday, May 1, 2019

eSilicon Tapes Out 7nm 400G Gearbox/Retimer Test ASIC

eSilicon announced the tapeout of a 7nm test ASIC that supports 400G gearbox and retimer functionality. Fabrication is expected in September.

A gearbox converts multiple serial data streams at one rate to multiple streams at another rate. Serial-to-parallel and parallel-to-serial converters (SerDes) are critical to this functionality. A retimer improves signal integrity by equalizing, retiming and re-conditioning the received data to extend reach.

The test ASIC includes four lanes of eSilicon’s long-reach 112 Gbps SerDes and eight lanes of its long-reach 56 Gbps SerDes. The eSilicon SerDes IP is integrated with media access control (MAC), forward error correction (FEC) and gearbox IP from Precise-ITC. The test ASIC is designed to allow customers to evaluate eSilicon’s SerDes IP and the Precise E-pak Ethernet IP in a test vehicle that is representative of a real-life application. It features long reach and low power as well as low latency for time-critical applications, such as high-performance computing. The technology in the chip can be used as the basis for developing 400G and 800G systems.

“This new test ASIC will open up new opportunities for our customers,” said Hugh Durdan, vice president, strategy and products at eSilicon. “We employed the latest release of our StarDesigner√§ 7nm flow for this design. Thanks to the global, early analysis of integration challenges delivered by the flow, we were able to meet all performance parameters for this design and tape out on schedule.”

https://www.esilicon.com/

eSilicon to move its ASIC and IP design work into Google Cloud

eSilicon will move all of its ASIC and IP design to Google Cloud Platform (GCP) this calendar year.

eSilicon has been running a hybrid on-premise/cloud environment for approximately the last 18 months, with ASIC design running on premise and IP design running primarily on GCP. This new agreement paves the way for a complete migration of all design activity to GCP.

“Moving to the cloud provides the flexibility to build the right compute environment for each design project, resulting in improvements in time-to-market and design quality,” said Mike Gianfagna, vice president of marketing at eSilicon.

Thursday, September 20, 2018

ECOC 2018: eSilicon to show 7nm 56G PAM4 long-reach SerDes

eSilicon plans to demonstrate the silicon performance of its 7nm 56G long-reach SerDes during ECOC 2018 (Anritsu booth #408).

eSilicon will show a periodic pattern generator (PPG)-to-chip live demo with different backplane reaches. Specifically, the demonstration will show 56G PAM4 data transfer running at 56Gb/s over two different BERTSCOPE channels with two different reaches, both driven by the Anritsu MP1900A Signal Quality Analyzer-R using a passive and an active PAM4 combiner. The demo with Anritsu is significant because it will show how it is possible to leverage TX finite impulse response (FIR) capabilities to increase performance and improve power figure of merit (FOM) and functionality. A key feature is high insertion loss tolerance with low bit-error rates to support increased bandwidth in legacy equipment.

“To obtain such reach and effectively stress the PAM4 SerDes receiver, it is very important to be able to generate an original extremely high-quality signal, and include equalization and stress tools for full control of the TX side. During the bring-up period, a flexible solution like Anritsu’s MP1900A is the best choice for an interoperability test,” said Anritsu EMEA Wireline Marketing Director Alessandro Messina.