Showing posts with label Xilinx. Show all posts
Showing posts with label Xilinx. Show all posts

Thursday, July 30, 2020

Xilinx sees strength in data center product and some order acceleration

Xilinx reported revenues of $727 million for the first quarter of its fiscal year 2021,  exceeding initial guidance and in-line with revised guidance. GAAP net income for the quarter was $94 million, or $0.38 per diluted share. Non-GAAP net income was $160 million, or $0.65 per diluted share.

The company noted record Data Center Group (DCG) revenue, with 10% sequential and 104% annual growth. Wireless Group (WWG) revenue increased 27% sequentially.

“Our fiscal Q1 revenue was well above the initial guidance despite ongoing business challenges from COVID-19 and global trade issues,” said Xilinx president and CEO Victor Peng. “Results were driven by strength in the Data Center Group (DCG), Wired and Wireless Group (WWG), and the Industrials market, offsetting expected headwinds in consumer-oriented end markets, including Automotive and Broadcast. The outperformance was due to a combination of strength in multiple end markets, as well as some order acceleration driven by recent additional U.S. government trade restrictions on sales of certain Xilinx products to some customers based, or with operations, in China.”

http://investor.xilinx.com/

Monday, June 29, 2020

Xilinx raises its revenue guidance

Xilinx raised the range of its prior guidance for its first quarter of fiscal 2021 ended June 27, 2020. The new expectations are as follows:

“While we have seen some COVID-19 related impacts during the June quarter, our business has generally performed well overall, with stronger than expected revenues in our Wired and Wireless Group and Data Center Group more than offsetting weaker than expected revenues in our consumer-oriented end markets, including automotive, broadcast, and consumer. A portion of the revenue strength in the quarter was due to customers accelerating orders following recent changes to the U.S. government restrictions on sales of certain of our products to international customers,” said Victor Peng, Xilinx’s President and Chief Executive Officer.

“Given our preliminary assessment of the expected financial results in the June quarter, we are raising the midpoint for revenue and narrowing our overall guidance ranges. Furthermore, we are updating our expected tax rate for the June quarter to include the prior and current year potential impacts of the Altera Corp. v. Commissioner tax case, a third-party legal proceeding concerning related-party R&D cost sharing arrangements and stock-based compensation. The potential impact for prior years is approximately $57 million while the impact to the fiscal 2021 expected tax rate is an additional 1%-2%.”

Tuesday, May 26, 2020

Xilinx spins 20-nm, radiation-tolerant, space-grade FPGAs

Xilinx introduced a 20-nanometer (nm) space-grade FPGA, offering full radiation tolerance and ultra-high throughput and bandwidth performance for satellite and space applications.

The new 20nm Radiation Tolerant (RT) Kintex UltraScale XQRKU060 FPGA provides true unlimited on-orbit reconfiguration, over a 10x increase in digital signal processing (DSP) performance – ideal for payload applications – and full radiation tolerance across all orbits.

The XQRKU060 offers rich DSP capabilities optimized for dense power-efficient compute. It is equipped with 2,760 UltraScale DSP slices and provides up to 1.6 TeraMACs of signal processing compute, more than a 10X increase compared to the prior generation, as well as dramatic efficiency gains for floating point computations. The increased compute capability in space is paired with massive I/O bandwidth from 32 high-speed transceivers (SerDes) that can run up to 12.5Gbps to deliver 400Gbps aggregate bandwidth.

The XQRKU060 also features robust 40x40mm ceramic packaging capable of withstanding vibrations and handling during launch as well as radiation effects in harsh orbit environments. The architecture features an innovative design for single event effects (SEE) mitigation thereby meeting the industry requirements for all orbits, including low earth orbit (LEO), medium earth orbit (MEO), geosynchronous orbit (GEO), and deep space missions.

“With our extensive history in developing leading-edge, radiation tolerant technology and deploying this in reliable space-grade solutions, Xilinx continues its lead with the launch of the world’s most advanced process node for space,” said Minal Sawant, space systems architect, Aerospace and Defense Vertical Marketing, at Xilinx. “The 20nm RT Kintex UltraScale FPGA is breaking industry standards and setting a new benchmark for meeting the high compute requirements of high bandwidth payloads, space exploration and research missions.”

Wednesday, April 22, 2020

Xilinx posts quarterly revenue of $756 million

Xilinx announced revenues of $3.16 billion for fiscal year 2020, up 3% from the prior fiscal year. Revenues were $756 million for the fourth quarter of fiscal year 2020, up 5% from the prior quarter and down 9% year over year.

GAAP net income for fiscal year 2020 was $793 million, or $3.11 per diluted share. Non-GAAP net income for fiscal year 2020 was $853 million, or $3.35 per diluted share. GAAP net income for the March quarter was $162 million, or $0.65 per diluted share. Non-GAAP net income for the March quarter was $193 million, or $0.78 per diluted share.

“Despite our fiscal 2020 being uniquely challenging, particularly related to the US trade-related restrictions with Huawei as well as some COVID-19 impact during our Q4, we were able to deliver another record year with revenue of $3.16 billion, a 3% increase over fiscal 2019,” said Xilinx president and CEO Victor Peng. “The strength and diversity of our business were reflected in the results of our fiscal fourth quarter with strong sequential growth in both revenue and profitability.”

“There remains a high degree of uncertainty in the global business environment given the impact of COVID-19 which creates challenges with visibility beyond the near term. Therefore, we believe it is prudent to provide only quarterly guidance at this time. We will continue to closely monitor business conditions. Lastly, I want to thank our employees for their continued focus and commitment in these challenging times.”

The Xilinx Board of Directors declared a quarterly cash dividend of $0.38 per outstanding share of common stock payable on June 3, 2020 to all stockholders of record at the close of business on May 13, 2020. The declared dividend represents a 2.7% increase over the prior quarter’s dividend and reflects Xilinx’s commitment to growing the dividend.

http://www.xilinx.com

Wednesday, April 15, 2020

Samsung Electronics picks Xilinx ACAP

Samsung Electronics Co. will use the Xilinx Versal adaptive compute acceleration platform (ACAP) for worldwide 5G commercial deployments.

Xilinx Versal ACAPs provide a universal, flexible and scalable platform that can address multiple operator requirements across multiple geographies. The devices can be used to perform the real-time, low-latency signal processing demanded by beamforming algorithms. The AI Engines, which are part of the Versal AI Core series, are comprised of a tiled array of vector processors.

“Samsung has been working closely with Xilinx, paving the way for enhancing our 5G technical leadership and opening up a new era in 5G,” said Jaeho Jeon, executive vice president and head of R&D, Networks business, Samsung Electronics. “Taking a step further by applying Xilinx’s new advanced platform to our solutions, we expect to increase 5G performance and accelerate our leadership position in the global market.”

“Samsung is a trailblazer when it comes to 5G innovation and we are excited to play an essential role in its 5G commercial deployments,” said Liam Madden, executive vice president and general manager, Wired and Wireless Group, Xilinx. “Versal ACAPs will provide Samsung with the superior signal processing performance and adaptability needed to deliver an exceptional 5G experience to its customers now and into the future.”

The first Versal ACAP devices have been shipping to early access customers and will be generally available in the Q4 2020 timeframe.

Thursday, April 9, 2020

Xilinx appoints Brice Hill as CFO

Xilinx appointed Brice Hill to the position of executive vice president and chief financial officer (CFO), effective immediately. He joins Xilinx from a 25-year tenure at Intel Corporation, where he most recently served as the CFO and COO, Technology, Systems and Core Engineering Group, managing all financial aspects of the company’s manufacturing, research and development, and product engineering operations.

Prior to that, Hill was Corporate Vice President of Corporate Strategy and Business Unit finance, including the Data Center, PC, and IoT business units. Hill had also previously held senior finance roles in capacity strategy, PC desktop and chipsets, and the data center at Intel.

Tuesday, January 21, 2020

Xilinx files patent infringement complaint against Analog Devices

Xilinx filed a patent infringement lawsuit against Analog Devices, asserting infringement of eight United States patents in the United States District Court for the District of Delaware. The filing came as a counterclaim to the an existing lawsuit between the firms.

Xilinx said its lawsuit details the unauthorized use by Analog Devices of certain Xilinx technologies involving serializers/deserializers (SerDes), high-speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), as well as mixed-signal devices targeting 5G and other markets. In addition to seeking damages, Xilinx is requesting that Analog Devices be enjoined from selling, offering to sell, or importing into the United States, products that infringe Xilinx’s asserted patents.

Wednesday, October 2, 2019

Xilinx intros Unified Software Platform for developers

At its second annual XDF event in San Jose, California, Xilinx introduced a unified developer software platform to drive applications powered by its programmable silicon.

Xilinx said it spent five years and a total of 1,000 man years to create the new platform, called Vitis (pronounced VÄ«-tis), which tailors the Xilinx hardware architecture to the software or algorithmic code without the need for hardware expertise.

The Vitis platform was designed to plug into common software developer tools and uses open source libraries. The base layer is the Vitis target platform, which includes a board and preprogrammed I/O. The second layer, called the Vitis core development kit, encompasses the open-source Xilinx runtime library to manage the data movement between different domains, including the subsystems, the AI Engine in the forthcoming Versal ACAP™, as well as an external host, if required. This layer also includes the core development tools such as compilers, analyzers and debuggers. While Xilinx provides a world-class design environment, these tools are designed to integrate seamlessly with industry-standard build systems and development environments. In the third layer are more than 400 optimized and open-source applications across eight Vitis libraries.

"With exponentially increasing compute needs, engineers and scientists are often limited by the fixed nature of silicon," said Victor Peng, president and chief executive officer, Xilinx. "Xilinx has created a singular environment that enables programmers and engineers from all disciplines to co-develop and optimize both their hardware and software, using the tools and frameworks they already know and understand. This means that they can adapt their hardware architecture to their application without the need for new silicon."


Wednesday, August 21, 2019

Xilinx's Virtex UltraScale+ FPGA boasts 35 billion transistors

Xilinx has expanded its 16nm Virtex UltraScale+ family to now include the world's largest FPGA — the Virtex UltraScale+ VU19P.

The new VU19P FPGA boasts 35 billion transistors, the highest logic density and I/O count on a single device, according to Xilinx. The device could be used for enabling emulation and prototyping of tomorrow's most advanced ASIC and SoC technologies, as well as test, measurement, compute, networking, aerospace and defense-related applications.

The VU19P FPGA features 9 million system logic cells, up to 1.5 terabits per-second of DDR4 memory bandwidth and up to 4.5 terabits per-second of transceiver bandwidth, and over 2,000 user I/Os. It is 1.6X larger than its predecessor and what was previously the industry's largest FPGA — the 20 nm Virtex UltraScale 440 FPGA. 

"The VU19P enables developers to accelerate hardware validation and begin software integration before their ASIC or SoC is available," said Sumit Shah, senior director, product line marketing and management, Xilinx. "This is our third generation of world-record FPGAs. First was the Virtex-7 2000T, followed by the Virtex UltraScale VU440, and now the Virtex UltraScale+ VU19P. But this is more than silicon technology; we're providing robust and proven tool flows and IP to support it."

"Arm relies on Xilinx devices as part of our process for validating our next-generation processor IP and SoC technology," said Tran Nguyen, director of design services, Arm. "The new VU19P will further enable Arm, and many others in our ecosystem, to accelerate the design, development and validation of our most ambitious roadmap technologies."

The VU19P will be generally available in the fall of 2020.

https://www.xilinx.com/news/press/2019/xilinx-announces-the-world-s-largest-fpga-featuring-9-million-system-logic-cells.html

Wednesday, July 31, 2019

Xilinx completes Solarflare acquisition -- SmartNICs

Xilinx completed its acquisition of Solarflare, a provider of high-performance, low latency networking solutions for customers spanning FinTech to cloud computing. Financial terms were not disclosed. The deal was first announced in April.

Earlier this year, the two companies demonstrated a single-chip FPGA-based 100Gb SmartNIC, processing 100 million packets per-second receive and transmit, all at less than 75 watts.

Xilinx to acquire Solarflare for SmartNIC solutions

Xilinx agreed to acquire Solarflare Communications, a provider of high-performance, low latency networking solutions for customers spanning FinTech to cloud computing. Financial terms were not disclosed.

Xilinx said the acquisition enables it to combine its FPGA, MPSoC and ACAP solutions with Solarflare's ultra-low latency network interface card (NIC) technology and Onload application acceleration software. The target is new converged SmartNIC solutions, accelerating Xilinx's "data center first" strategy.


Xilinx and Solarflare have been collaborating on advanced networking technology for the last two years, with Xilinx becoming a strategic investor in 2017. The two companies recently demonstrated their first joint solution – a single-chip FPGA-based 100G SmartNIC, processing 100 million packets per-second receive and transmit, all at less than 75 watts.

Tuesday, May 7, 2019

Ingram Micro adds Xilinx accelerator cards to catalog

Ingram Micro has been named a primary distributor for Xilinx's new Alveo data center accelerator cards.

Ingram Micro will distribute the Xilinx cards to channel partners throughout the United States. Xilinx said channel partners will help speed the deployment of the cards in industry standard servers, ultimately optimizing the solutions for customers’ shifting data center workloads, new standards and evolving algorithms.


  • In October, as part of its updated data center strategy, Xilinx announced its own portfolio of accelerator cards for industry-standard servers in cloud and on-premise data centers. The new Alveo PCIe cards are powered by the Xilinx UltraScale+ FPGA, are available now for production orders. Customers can reconfigure the hardware, enabling them to optimize for shifting workloads, new standards, and updated algorithms.


Wednesday, April 24, 2019

Xilinx to acquire Solarflare for SmartNIC solutions

Xilinx agreed to acquire Solarflare Communications, a provider of high-performance, low latency networking solutions for customers spanning FinTech to cloud computing. Financial terms were not disclosed.

Xilinx said the acquisition enables it to combine its FPGA, MPSoC and ACAP solutions with Solarflare's ultra-low latency network interface card (NIC) technology and Onload application acceleration software. The target is new converged SmartNIC solutions, accelerating Xilinx's "data center first" strategy.

Xilinx and Solarflare have been collaborating on advanced networking technology for the last two years, with Xilinx becoming a strategic investor in 2017. The two companies recently demonstrated their first joint solution – a single-chip FPGA-based 100G SmartNIC, processing 100 million packets per-second receive and transmit, all at less than 75 watts.

"The Solarflare team has worked very closely with Xilinx on next-generation networking technology and business collaboration since Xilinx became a strategic investor," says Russell Stern, chief executive officer, Solarflare. "Our shared vision for the future of data center and cloud computing and the integration of our respective technologies makes this acquisition the ideal next step for our customers, employees, and investors, as well as the broader data center industry."

"Solarflare has been a pioneer in key areas such as high-speed Ethernet, application acceleration, and NVMe-over-fabrics, which are the critical components needed to build the next generation of SmartNICs for cloud and enterprise technologies," says Salil Raje, executive vice president and general manager, Data Center Group, Xilinx.  "Acquiring Solarflare brings Xilinx both market-leading technology and exceptional engineering talent with expertise in networking hardware, software, firmware and drivers. We are very excited about the possibilities with Solarflare as part of the Xilinx family to enable the adaptable, intelligent world."


Tuesday, March 12, 2019

First edge infrastructure dev platform for 7nm Arm Neoverse

Arm, Cadence Design Systems, and Xilinx introduced a development platform cloud-to-edge infrastructure based on the new Arm Neoverse N1.

The Neoverse N1 System Development Platform (SDP) is based on TSMC’s 7nm FinFET process technology and is also the industry’s first 7nm infrastructure development platform enabling asymmetrical compute acceleration via the CCIX interconnect architecture/

The joint solution is available to hardware and software developers for hardware prototyping, software development, system validation, and performance profiling/tuning. It includes Cadence IP for CCIX, PCI Express (PCIe) Gen 4 and DDR4 PHY IP.

The SDP includes a Neoverse N1-based SoC with an operating frequency of up to 3GHz, full-sized caches and generous amounts of memory bandwidth with the latest optimized system IP. The robustness of the SDP is ideal for development, debug, performance optimization and workload analysis on a wide range of applications including those for machine learning (ML), artificial intelligence (AI) and data analytics.

“The new Neoverse platforms deliver the performance and efficiency required to enable the cloud-to-edge infrastructure for a world with a trillion connected devices. Our ongoing SDP collaboration with Cadence, TSMC, and Xilinx truly enables developers with the system development tools necessary to innovate and deliver optimized Neoverse-based designs,” stated Drew Henry, senior vice president and general manager, Infrastructure Line of Business, Arm.

Wednesday, February 20, 2019

Xilinx updates Zynq UltraScale+ RFSoC chip for 5G sub-6GHz

Xilinx has updated its Zynq UltraScale+ Radio Frequency (RF) System-on-Chip (SoC) portfolio for greater RF performance and scalability.

The new Zynq devices can cover the entire sub-6 gigahertz (GHz) spectrum, which is a critical need for next-generation 5G deployment. They support direct RF sampling of up to 5 giga-samples per-second (GS/S) 14-bit analog-to-digital converters (ADCs) and 10 GS/S 14-bit digital-to-analog converters (DACs), both up to 6 GHz of analog bandwidth.

The portfolio now includes:

  • Xilinx Zynq UltraScale+ RFSoC Gen 2: Sampling now with production scheduled for June 2019, this device meets regional deployment timelines in Asia and supports 5G New Radio.
  • Xilinx Zynq UltraScale+ RFSoC Gen 3: Provides full sub-6GHz direct-RF support, extended millimeter wave interface, and up to 20 percent power reduction in the RF data converter subsystem compared to the base portfolio. The product will be available in 2H 2019.

"We are committed to helping our customers accelerate innovation, and are especially excited to drive the development of adaptable, intelligent 5G infrastructure with these new, higher performing additions to the Zynq UltraScale+ RFSoC portfolio," said Liam Madden, executive vice president of hardware and systems product development, Xilinx. "Now with complete coverage of sub-6GHz spectrum bands, it will give our customers even more of a competitive advantage by allowing them to accelerate the design and development of next-gen systems today."

Wednesday, January 23, 2019

Xilinx posts record sales of $800M, up 34% yoy

Xilinx reported record revenues of $800 million for the third quarter of fiscal year 2019, up 7% from the prior quarter and up 34% year over year. GAAP net income for the December quarter was $239 million, or $0.93 per diluted share.  Non-GAAP net income for the December quarter was $237 million, or $0.92 per diluted share.

"I am very excited to report yet another record revenue and earnings quarter.  During the third fiscal quarter, we delivered revenues of $800 million, representing 34% year over year growth. Based on the guidance we are providing for the fiscal fourth quarter, we expect to exceed $3 billion in annual revenues for the first time in our history. In addition to the robust revenue growth, we also demonstrated strong profitability by posting over 60% growth in non-GAAP operating income and over 40% growth in non-GAAP diluted earnings per share year over year.  We continue to execute to our strategy and drive growth across our portfolio," said Victor Peng, President and Chief Executive Officer.

Thursday, January 17, 2019

Baidu employs Xilix for edge acceleration board

Baidu has developed an edge acceleration computing solution enabled by Xilinx and targetted at edge application products such as smart-video security surveillance solutions, advanced-driver-assistance systems and next-generation robots.

The Baidu EdgeBoard is a turn-key solution that can be configured and customized as part of the Baidu Brain AI Hardware Platform initiative.

The Baidu Brain AI Hardware Platform is part of the Baidu Brain AI capabilities open platform, encompassing Baidu's open computing services and hardware and software products for edge artificial intelligence (AI) applications.

EdgeBoard is based on the Xilinx Zynq UltraScale+ MPSoC, which integrates real-time processors with programmable logic.

"Xilinx offers the world's leading adaptive chips and development support. The flexible EdgeBoard we built based on Xilinx is designed to enable developers and engineers to quickly leverage Baidu-proven technology or deploy self-defined models, enabling faster deployment," said Youping Yu, general manager of Baidu's AI ecosystem division. "This is the ideal acceleration engine to enable Baidu Brain to broadly serve Chinese edge AI developers."

"We are very excited to be selected as the AI technology for the Baidu Brain AI Hardware Platform," said Freddy Engineer, corporate vice president, global data center sales, Xilinx. "The massive and open ecosystem being built by Baidu will accelerate the innovation of edge AI across China, resulting in products and solutions that will improve the way we work and live."

http://ai.baidu.com/tech/hardware/deepkit.

Tuesday, October 2, 2018

Xilinx looks beyond FPGAs with Adaptive Compute Acceleration Platform

At its second annual Xilinx Developer Forum (XDF) in San Jose, Xilinx unveiled strategic moves beyond its mainstay field-programmable gate array (FPGAs) with the introduction of its own accelerator line cards and, more significantly, a new Adaptive Compute Acceleration Platform (ACAP).

Xilinx, which got its start in 1984 and now sells a broad range of FPGAs and complex programmable logic devices (CPLDs), is transforming itself into a higher-value platform provider not only for existing workloads but for new domains, especially AI, hyperscale cloud data centers, autonomous vehicles, and 5G infrastructure.

In a keynote at the event, Victor Peng Xilinx's new CEO, Victor Peng, who took over the leadership position in January from Moshe Gavriel, said that a transformation is being driven by the rapid rise in overall compute workloads hitting just as Moore's Law is slowing down. Xilinx's chief advantages have been flexibility and performance compared to custom ASICs. As we move into the era of machine learning and artificial intelligence, Xilinx is positioning itself as a better alternative to CPUs (especially Intel), GPUs (especially NVIDIA), and the custom silicon developed by hyperscale cloud giants (especially Google and soon likely others).

As part of its updated data center strategy, Xilinx is announcing its own portfolio of accelerator cards for industry-standard servers in cloud and on-premise data centers. The new Alveo PCIe cards are powered by the Xilinx UltraScale+ FPGA, are available now for production orders. Customers can reconfigure the hardware, enabling them to optimize for shifting workloads, new standards, and updated algorithms.

Xilinx says performance when used in machine learning frameworks will be great. An Alveo U250 card increases real-time inference throughput by 20X versus high-end CPUs, and more than 4X for sub-two-millisecond low-latency applications versus fixed-function accelerators like high-end GPUs.  Alveo is supported by an ecosystem of partners and OEMs including Algo-Logic Systems Inc, Bigstream, BlackLynx Inc., CTAccel, Falcon Computing, Maxeler Technologies, Mipsology, NGCodec, Skreens, SumUp Analytics, Titan IC, Vitesse Data, VYUsync and Xelera Technologies.

"The launch of Alveo accelerator cards further advances Xilinx's transformation into a platform company, enabling a growing ecosystem of application partners that can now innovate faster than ever before," said Manish Muthal, vice president, data center, Xilinx. "We are seeing strong customer interest in Alveo accelerators and are delighted to partner with our application ecosystem to deliver production-deployable solutions based on Alveo to our customers."

The second big announcement from XDF was the unveiling Versal adaptive compute acceleration platform (ACAP), a fully software-programmable, heterogeneous compute platform that combines Scalar Engines, Adaptable Engines, and Intelligent Engines. Xilinx is claiming dramatic performance improvements of up to 20X over today's FPGAs, and over 100X over today's fastest CPUs. Target applications include Data Center, wired network, 5G wireless, and automobile driver assist applications.

The Versal ACAP is built on TSMC's 7-nanometer FinFET process technology. It combines software programmability with domain-specific hardware acceleration and the adaptability/

Xilinx already has plans for six series of devices in the Versal family.  This includes the Versal Prime series, Premium series and HBM series, which are designed to deliver performance, connectivity, bandwidth, and integration for the most demanding applications. It also includes the AI Core series, AI Edge series, and AI RF series, which feature the breakthrough AI Engine. The AI Engine is a new hardware block designed to address the emerging need for low-latency AI inference for a wide variety of applications and also supports advanced DSP implementations for applications like wireless and radar. It is tightly coupled with the Versal Adaptable Hardware Engines to enable whole application acceleration, meaning that both the hardware and software can be tuned to ensure maximum performance and efficiency.

"With the explosion of AI and big data and the decline of Moore's Law, the industry has reached a critical inflection point. Silicon design cycles can no longer keep up with the pace of innovation," says Peng. "Four years in development, Versal is the industry's first ACAP. We uniquely designed it to enable all types of developers to accelerate their whole application with optimized hardware and software and to instantly adapt both to keep pace with rapidly evolving technology. It is exactly what the industry needs at the exact moment it needs it."

The Versal AI Core series, which is optimized for cloud, networking, and autonomous technology, has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. It also incorporates more than 1.9 million system logic cells combined with more than 130Mb of UltraRAM, up to 34Mb of block RAM, and 28Mb of distributed RAM and 32Mb of new Accelerator RAM blocks, which can be directly accessed from any engine and is unique to the Versal AI series' – all to support custom memory hierarchies. The series also includes PCIe Gen4 8-lane and 16-lane, and CCIX host interfaces, power-optimized 32G SerDes, up to 4 integrated DDR4 memory controllers, up to 4 multi-rate Ethernet MACs, 650 high-performance I/Os for MIPI D-PHY, NAND, storage-class memory interfacing and LVDS, plus 78 multiplexed I/Os to connect external components and more than 40 HD I/Os for 3.3V interfacing. All of this is interconnected by a state-of-the-art network-on-chip (NoC) with up to 28 master/slave ports, delivering multi-terabit per-second bandwidth at low latency combined with power efficiency and native software programmability.  The full product table is now available.

The Versal Prime series is designed for broad applicability across multiple markets and is optimized for connectivity and in-line acceleration of a diverse set of workloads. This mid-range series is made up of nine devices, each including dual-core Arm Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 4,000 DSP engines optimized for high-precision floating point with low latency. It also incorporates more than 2 million system logic cells combined with more than 200Mb of UltraRAM, greater than 90Mb of block RAM, and 30Mb of distributed RAM to support custom memory hierarchies. The series also includes PCIe® Gen4 8-lane and 16-lane, and CCIX host interfaces, power-optimized 32 gigabits-per-second SerDes and mainstream 58 gigabits-per-second PAM4 SerDes, up to 6 integrated DDR4 memory controllers, up to 4 multi-rate Ethernet MACs, 700 high-performance I/Os for MIPI D-PHY, NAND, and storage-class memory interfaces and LVDS, plus 78 multiplexed I/Os to connect external components, and greater than 40 HD I/O for 3.3V interfacing. All of this is interconnected by a state-of-the-art network-on-chip (NoC) with up to 28 master/slave ports, delivering multi-terabits per-second bandwidth at low latency combined with power efficiency and native software programmability. The full product table is available now.

Thursday, January 4, 2018

Xilinx names Victor Peng as its new CEO

Xilinx named Victor Peng as its next president and chief executive officer, replacing Moshe Gavrielov, who will step down as CEO and from the board of directors on January 28th.

Since joining the company in 2008, Peng has spearheaded industry-leading strategy and technical shifts across the company’s portfolio of products and services, resulting in three consecutive generations of core product leadership and significant technology breakthroughs in integration and programming.  Most recently,

Peng joined Xilinx in 2009 and currently serves as Chief Operating Officer. He was appointed as a member of the board of directors in October 2017. Before joining Xilinx, Peng served as corporate vice president of the graphics products group (GPG) silicon engineering at AMD.

Tuesday, September 12, 2017

Huawei picks Xilinx FPGAs for Accelerated Cloud Server

Huawei has selected Xilinx Virtex UltraScale+ FPGAs to power their first FP1 instance as part of a new accelerated cloud service. The Huawei FPGA Accelerated Cloud Server (FACS) is a platform that enables users to develop, deploy and publish new FPGA-based services and applications on Huawei Public Cloud.

Xilinx said its FPGAs can provide a 10-50x speed-up for compute intensive cloud applications such as machine learning, data analytics, and video processing.  Xilinx FPGAs can be reconfigured in less than a second to a different design that is hardware optimized for its next workload.

"The Huawei FACS is a fully integrated hardware and software platform offering developer-to-deployment support with best-in-class industry tool chains and access to Huawei's significant FPGA engineering expertise," said Steve Langridge, Director, Central Hardware Institute, Huawei Canada Research Center.

The FPGA Accelerated Cloud Server now available on the Huawei Public Cloud.

http://www.hwclouds.com/product/fcs.html
http://www.huaweicloud.com

Monday, July 10, 2017

Baidu deploys Xilinx FPGAs for cloud acceleration

Xilinx announced that Baidu has deployed Xilinx FPGA-based application acceleration services into its public cloud, specifically for the Baidu FPGA Cloud Server, a new service that leverages Xilinx Kintex FPGAs, tools and the software required for hardware-accelerated data centre applications such as machine learning and data security.

The Baidu FPGA Cloud Server provides a complete FPGA-based hardware and software development environment, including hardware and software design examples, and is designed to help users quickly develop and migrate applications with reduced development costs.

The Baidu service is based on each FPGA instance serving as a dedicated acceleration platform that is not shared between instances or users. The design examples provided services including cover deep learning acceleration, encryption and decryption.

Xilinx claims that FPGA-enabled servers can deliver a 10x to 80x performance per watt advantage compared to CPU-only servers. In addition, as they are dynamically reconfigurable, Xilinx FPGAs can support a range of workloads, including machine learning, data analytics, security and video processing.



  • Separately, Baidu announced a partnership with Microsoft for its new open source autonomous driving platform, Apollo. Baidu unveiled Apollo in April, featuring cloud services, software and reference hardware/vehicle platforms, and expects the technology will be running on roads by late 2020.
  • In addition, Conexant, a provider of audio and voice technology solutions, announced it was collaborating with Baidu to release development kits and reference designs for device makers to develop far-field voice-enabled artificial intelligent (AI) devices running on Baidu's DuerOS platform. The development kits and reference designs will feature Conexant's CX20924 4-microphone and CX20921 2-microphone voice input processing solutions and DuerOS, a conversation-based AI system that enables access to a voice-activated digital assistant for mobile phones, TVs and other devices.