Showing posts with label Xilinx. Show all posts
Showing posts with label Xilinx. Show all posts

Tuesday, May 7, 2019

Ingram Micro adds Xilinx accelerator cards to catalog

Ingram Micro has been named a primary distributor for Xilinx's new Alveo data center accelerator cards.

Ingram Micro will distribute the Xilinx cards to channel partners throughout the United States. Xilinx said channel partners will help speed the deployment of the cards in industry standard servers, ultimately optimizing the solutions for customers’ shifting data center workloads, new standards and evolving algorithms.


  • In October, as part of its updated data center strategy, Xilinx announced its own portfolio of accelerator cards for industry-standard servers in cloud and on-premise data centers. The new Alveo PCIe cards are powered by the Xilinx UltraScale+ FPGA, are available now for production orders. Customers can reconfigure the hardware, enabling them to optimize for shifting workloads, new standards, and updated algorithms.


Wednesday, April 24, 2019

Xilinx to acquire Solarflare for SmartNIC solutions

Xilinx agreed to acquire Solarflare Communications, a provider of high-performance, low latency networking solutions for customers spanning FinTech to cloud computing. Financial terms were not disclosed.

Xilinx said the acquisition enables it to combine its FPGA, MPSoC and ACAP solutions with Solarflare's ultra-low latency network interface card (NIC) technology and Onload application acceleration software. The target is new converged SmartNIC solutions, accelerating Xilinx's "data center first" strategy.

Xilinx and Solarflare have been collaborating on advanced networking technology for the last two years, with Xilinx becoming a strategic investor in 2017. The two companies recently demonstrated their first joint solution – a single-chip FPGA-based 100G SmartNIC, processing 100 million packets per-second receive and transmit, all at less than 75 watts.

"The Solarflare team has worked very closely with Xilinx on next-generation networking technology and business collaboration since Xilinx became a strategic investor," says Russell Stern, chief executive officer, Solarflare. "Our shared vision for the future of data center and cloud computing and the integration of our respective technologies makes this acquisition the ideal next step for our customers, employees, and investors, as well as the broader data center industry."

"Solarflare has been a pioneer in key areas such as high-speed Ethernet, application acceleration, and NVMe-over-fabrics, which are the critical components needed to build the next generation of SmartNICs for cloud and enterprise technologies," says Salil Raje, executive vice president and general manager, Data Center Group, Xilinx.  "Acquiring Solarflare brings Xilinx both market-leading technology and exceptional engineering talent with expertise in networking hardware, software, firmware and drivers. We are very excited about the possibilities with Solarflare as part of the Xilinx family to enable the adaptable, intelligent world."


Tuesday, March 12, 2019

First edge infrastructure dev platform for 7nm Arm Neoverse

Arm, Cadence Design Systems, and Xilinx introduced a development platform cloud-to-edge infrastructure based on the new Arm Neoverse N1.

The Neoverse N1 System Development Platform (SDP) is based on TSMC’s 7nm FinFET process technology and is also the industry’s first 7nm infrastructure development platform enabling asymmetrical compute acceleration via the CCIX interconnect architecture/

The joint solution is available to hardware and software developers for hardware prototyping, software development, system validation, and performance profiling/tuning. It includes Cadence IP for CCIX, PCI Express (PCIe) Gen 4 and DDR4 PHY IP.

The SDP includes a Neoverse N1-based SoC with an operating frequency of up to 3GHz, full-sized caches and generous amounts of memory bandwidth with the latest optimized system IP. The robustness of the SDP is ideal for development, debug, performance optimization and workload analysis on a wide range of applications including those for machine learning (ML), artificial intelligence (AI) and data analytics.

“The new Neoverse platforms deliver the performance and efficiency required to enable the cloud-to-edge infrastructure for a world with a trillion connected devices. Our ongoing SDP collaboration with Cadence, TSMC, and Xilinx truly enables developers with the system development tools necessary to innovate and deliver optimized Neoverse-based designs,” stated Drew Henry, senior vice president and general manager, Infrastructure Line of Business, Arm.

Wednesday, February 20, 2019

Xilinx updates Zynq UltraScale+ RFSoC chip for 5G sub-6GHz

Xilinx has updated its Zynq UltraScale+ Radio Frequency (RF) System-on-Chip (SoC) portfolio for greater RF performance and scalability.

The new Zynq devices can cover the entire sub-6 gigahertz (GHz) spectrum, which is a critical need for next-generation 5G deployment. They support direct RF sampling of up to 5 giga-samples per-second (GS/S) 14-bit analog-to-digital converters (ADCs) and 10 GS/S 14-bit digital-to-analog converters (DACs), both up to 6 GHz of analog bandwidth.

The portfolio now includes:

  • Xilinx Zynq UltraScale+ RFSoC Gen 2: Sampling now with production scheduled for June 2019, this device meets regional deployment timelines in Asia and supports 5G New Radio.
  • Xilinx Zynq UltraScale+ RFSoC Gen 3: Provides full sub-6GHz direct-RF support, extended millimeter wave interface, and up to 20 percent power reduction in the RF data converter subsystem compared to the base portfolio. The product will be available in 2H 2019.

"We are committed to helping our customers accelerate innovation, and are especially excited to drive the development of adaptable, intelligent 5G infrastructure with these new, higher performing additions to the Zynq UltraScale+ RFSoC portfolio," said Liam Madden, executive vice president of hardware and systems product development, Xilinx. "Now with complete coverage of sub-6GHz spectrum bands, it will give our customers even more of a competitive advantage by allowing them to accelerate the design and development of next-gen systems today."

Wednesday, January 23, 2019

Xilinx posts record sales of $800M, up 34% yoy

Xilinx reported record revenues of $800 million for the third quarter of fiscal year 2019, up 7% from the prior quarter and up 34% year over year. GAAP net income for the December quarter was $239 million, or $0.93 per diluted share.  Non-GAAP net income for the December quarter was $237 million, or $0.92 per diluted share.

"I am very excited to report yet another record revenue and earnings quarter.  During the third fiscal quarter, we delivered revenues of $800 million, representing 34% year over year growth. Based on the guidance we are providing for the fiscal fourth quarter, we expect to exceed $3 billion in annual revenues for the first time in our history. In addition to the robust revenue growth, we also demonstrated strong profitability by posting over 60% growth in non-GAAP operating income and over 40% growth in non-GAAP diluted earnings per share year over year.  We continue to execute to our strategy and drive growth across our portfolio," said Victor Peng, President and Chief Executive Officer.

Thursday, January 17, 2019

Baidu employs Xilix for edge acceleration board

Baidu has developed an edge acceleration computing solution enabled by Xilinx and targetted at edge application products such as smart-video security surveillance solutions, advanced-driver-assistance systems and next-generation robots.

The Baidu EdgeBoard is a turn-key solution that can be configured and customized as part of the Baidu Brain AI Hardware Platform initiative.

The Baidu Brain AI Hardware Platform is part of the Baidu Brain AI capabilities open platform, encompassing Baidu's open computing services and hardware and software products for edge artificial intelligence (AI) applications.

EdgeBoard is based on the Xilinx Zynq UltraScale+ MPSoC, which integrates real-time processors with programmable logic.

"Xilinx offers the world's leading adaptive chips and development support. The flexible EdgeBoard we built based on Xilinx is designed to enable developers and engineers to quickly leverage Baidu-proven technology or deploy self-defined models, enabling faster deployment," said Youping Yu, general manager of Baidu's AI ecosystem division. "This is the ideal acceleration engine to enable Baidu Brain to broadly serve Chinese edge AI developers."

"We are very excited to be selected as the AI technology for the Baidu Brain AI Hardware Platform," said Freddy Engineer, corporate vice president, global data center sales, Xilinx. "The massive and open ecosystem being built by Baidu will accelerate the innovation of edge AI across China, resulting in products and solutions that will improve the way we work and live."

http://ai.baidu.com/tech/hardware/deepkit.

Tuesday, October 2, 2018

Xilinx looks beyond FPGAs with Adaptive Compute Acceleration Platform

At its second annual Xilinx Developer Forum (XDF) in San Jose, Xilinx unveiled strategic moves beyond its mainstay field-programmable gate array (FPGAs) with the introduction of its own accelerator line cards and, more significantly, a new Adaptive Compute Acceleration Platform (ACAP).

Xilinx, which got its start in 1984 and now sells a broad range of FPGAs and complex programmable logic devices (CPLDs), is transforming itself into a higher-value platform provider not only for existing workloads but for new domains, especially AI, hyperscale cloud data centers, autonomous vehicles, and 5G infrastructure.

In a keynote at the event, Victor Peng Xilinx's new CEO, Victor Peng, who took over the leadership position in January from Moshe Gavriel, said that a transformation is being driven by the rapid rise in overall compute workloads hitting just as Moore's Law is slowing down. Xilinx's chief advantages have been flexibility and performance compared to custom ASICs. As we move into the era of machine learning and artificial intelligence, Xilinx is positioning itself as a better alternative to CPUs (especially Intel), GPUs (especially NVIDIA), and the custom silicon developed by hyperscale cloud giants (especially Google and soon likely others).

As part of its updated data center strategy, Xilinx is announcing its own portfolio of accelerator cards for industry-standard servers in cloud and on-premise data centers. The new Alveo PCIe cards are powered by the Xilinx UltraScale+ FPGA, are available now for production orders. Customers can reconfigure the hardware, enabling them to optimize for shifting workloads, new standards, and updated algorithms.

Xilinx says performance when used in machine learning frameworks will be great. An Alveo U250 card increases real-time inference throughput by 20X versus high-end CPUs, and more than 4X for sub-two-millisecond low-latency applications versus fixed-function accelerators like high-end GPUs.  Alveo is supported by an ecosystem of partners and OEMs including Algo-Logic Systems Inc, Bigstream, BlackLynx Inc., CTAccel, Falcon Computing, Maxeler Technologies, Mipsology, NGCodec, Skreens, SumUp Analytics, Titan IC, Vitesse Data, VYUsync and Xelera Technologies.

"The launch of Alveo accelerator cards further advances Xilinx's transformation into a platform company, enabling a growing ecosystem of application partners that can now innovate faster than ever before," said Manish Muthal, vice president, data center, Xilinx. "We are seeing strong customer interest in Alveo accelerators and are delighted to partner with our application ecosystem to deliver production-deployable solutions based on Alveo to our customers."

The second big announcement from XDF was the unveiling Versal adaptive compute acceleration platform (ACAP), a fully software-programmable, heterogeneous compute platform that combines Scalar Engines, Adaptable Engines, and Intelligent Engines. Xilinx is claiming dramatic performance improvements of up to 20X over today's FPGAs, and over 100X over today's fastest CPUs. Target applications include Data Center, wired network, 5G wireless, and automobile driver assist applications.

The Versal ACAP is built on TSMC's 7-nanometer FinFET process technology. It combines software programmability with domain-specific hardware acceleration and the adaptability/

Xilinx already has plans for six series of devices in the Versal family.  This includes the Versal Prime series, Premium series and HBM series, which are designed to deliver performance, connectivity, bandwidth, and integration for the most demanding applications. It also includes the AI Core series, AI Edge series, and AI RF series, which feature the breakthrough AI Engine. The AI Engine is a new hardware block designed to address the emerging need for low-latency AI inference for a wide variety of applications and also supports advanced DSP implementations for applications like wireless and radar. It is tightly coupled with the Versal Adaptable Hardware Engines to enable whole application acceleration, meaning that both the hardware and software can be tuned to ensure maximum performance and efficiency.

"With the explosion of AI and big data and the decline of Moore's Law, the industry has reached a critical inflection point. Silicon design cycles can no longer keep up with the pace of innovation," says Peng. "Four years in development, Versal is the industry's first ACAP. We uniquely designed it to enable all types of developers to accelerate their whole application with optimized hardware and software and to instantly adapt both to keep pace with rapidly evolving technology. It is exactly what the industry needs at the exact moment it needs it."

The Versal AI Core series, which is optimized for cloud, networking, and autonomous technology, has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. It also incorporates more than 1.9 million system logic cells combined with more than 130Mb of UltraRAM, up to 34Mb of block RAM, and 28Mb of distributed RAM and 32Mb of new Accelerator RAM blocks, which can be directly accessed from any engine and is unique to the Versal AI series' – all to support custom memory hierarchies. The series also includes PCIe Gen4 8-lane and 16-lane, and CCIX host interfaces, power-optimized 32G SerDes, up to 4 integrated DDR4 memory controllers, up to 4 multi-rate Ethernet MACs, 650 high-performance I/Os for MIPI D-PHY, NAND, storage-class memory interfacing and LVDS, plus 78 multiplexed I/Os to connect external components and more than 40 HD I/Os for 3.3V interfacing. All of this is interconnected by a state-of-the-art network-on-chip (NoC) with up to 28 master/slave ports, delivering multi-terabit per-second bandwidth at low latency combined with power efficiency and native software programmability.  The full product table is now available.

The Versal Prime series is designed for broad applicability across multiple markets and is optimized for connectivity and in-line acceleration of a diverse set of workloads. This mid-range series is made up of nine devices, each including dual-core Arm Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 4,000 DSP engines optimized for high-precision floating point with low latency. It also incorporates more than 2 million system logic cells combined with more than 200Mb of UltraRAM, greater than 90Mb of block RAM, and 30Mb of distributed RAM to support custom memory hierarchies. The series also includes PCIe® Gen4 8-lane and 16-lane, and CCIX host interfaces, power-optimized 32 gigabits-per-second SerDes and mainstream 58 gigabits-per-second PAM4 SerDes, up to 6 integrated DDR4 memory controllers, up to 4 multi-rate Ethernet MACs, 700 high-performance I/Os for MIPI D-PHY, NAND, and storage-class memory interfaces and LVDS, plus 78 multiplexed I/Os to connect external components, and greater than 40 HD I/O for 3.3V interfacing. All of this is interconnected by a state-of-the-art network-on-chip (NoC) with up to 28 master/slave ports, delivering multi-terabits per-second bandwidth at low latency combined with power efficiency and native software programmability. The full product table is available now.

Thursday, January 4, 2018

Xilinx names Victor Peng as its new CEO

Xilinx named Victor Peng as its next president and chief executive officer, replacing Moshe Gavrielov, who will step down as CEO and from the board of directors on January 28th.

Since joining the company in 2008, Peng has spearheaded industry-leading strategy and technical shifts across the company’s portfolio of products and services, resulting in three consecutive generations of core product leadership and significant technology breakthroughs in integration and programming.  Most recently,

Peng joined Xilinx in 2009 and currently serves as Chief Operating Officer. He was appointed as a member of the board of directors in October 2017. Before joining Xilinx, Peng served as corporate vice president of the graphics products group (GPG) silicon engineering at AMD.

Tuesday, September 12, 2017

Huawei picks Xilinx FPGAs for Accelerated Cloud Server

Huawei has selected Xilinx Virtex UltraScale+ FPGAs to power their first FP1 instance as part of a new accelerated cloud service. The Huawei FPGA Accelerated Cloud Server (FACS) is a platform that enables users to develop, deploy and publish new FPGA-based services and applications on Huawei Public Cloud.

Xilinx said its FPGAs can provide a 10-50x speed-up for compute intensive cloud applications such as machine learning, data analytics, and video processing.  Xilinx FPGAs can be reconfigured in less than a second to a different design that is hardware optimized for its next workload.

"The Huawei FACS is a fully integrated hardware and software platform offering developer-to-deployment support with best-in-class industry tool chains and access to Huawei's significant FPGA engineering expertise," said Steve Langridge, Director, Central Hardware Institute, Huawei Canada Research Center.

The FPGA Accelerated Cloud Server now available on the Huawei Public Cloud.

http://www.hwclouds.com/product/fcs.html
http://www.huaweicloud.com

Monday, July 10, 2017

Baidu deploys Xilinx FPGAs for cloud acceleration

Xilinx announced that Baidu has deployed Xilinx FPGA-based application acceleration services into its public cloud, specifically for the Baidu FPGA Cloud Server, a new service that leverages Xilinx Kintex FPGAs, tools and the software required for hardware-accelerated data centre applications such as machine learning and data security.

The Baidu FPGA Cloud Server provides a complete FPGA-based hardware and software development environment, including hardware and software design examples, and is designed to help users quickly develop and migrate applications with reduced development costs.

The Baidu service is based on each FPGA instance serving as a dedicated acceleration platform that is not shared between instances or users. The design examples provided services including cover deep learning acceleration, encryption and decryption.

Xilinx claims that FPGA-enabled servers can deliver a 10x to 80x performance per watt advantage compared to CPU-only servers. In addition, as they are dynamically reconfigurable, Xilinx FPGAs can support a range of workloads, including machine learning, data analytics, security and video processing.



  • Separately, Baidu announced a partnership with Microsoft for its new open source autonomous driving platform, Apollo. Baidu unveiled Apollo in April, featuring cloud services, software and reference hardware/vehicle platforms, and expects the technology will be running on roads by late 2020.
  • In addition, Conexant, a provider of audio and voice technology solutions, announced it was collaborating with Baidu to release development kits and reference designs for device makers to develop far-field voice-enabled artificial intelligent (AI) devices running on Baidu's DuerOS platform. The development kits and reference designs will feature Conexant's CX20924 4-microphone and CX20921 2-microphone voice input processing solutions and DuerOS, a conversation-based AI system that enables access to a voice-activated digital assistant for mobile phones, TVs and other devices.

Friday, March 17, 2017

Xilinx to Demo FPGAs in 400G Ethernet, FlexE

At this week's Optical Fiber Communications (OFC) Conference and Exhibition in Los Angeles Xilinx will debut a number of solutions for high speed data center interconnect (DCI) solutions.

Xilinx will participate in a 400GE multi-vendor network demo featuring the world's first standards-based 400GE MAC and PCS IP in a Xilinx Virtex UltraScale+™ VU9P FPGA. Showcasing the emerging 400GE standard interoperability between multiple vendors, the demo illustrates the Xilinx 400G solution connecting to a Finisar 400GE CFP8 module which in turn connects to a Spirent 400G test module in the Ethernet Alliance booth.

Xilinx will also showcase a complete FlexE 1.0 solution with bonding, sub-rating and channelization on its UltraScale+ FPGAs. This solution demonstrates how multiple clients can be transported using FlexE and highlights the ability of FlexE to carry larger data pipes and match them to transport links for optimal utilization of the link budget. This solution allows network operators to maximize optical performance and lower operating costs over existing infrastructure.

A third demo shows how LLDP packets can be snooped on transport line cards to allow a SDN controller to build a network topology for automation integral to data center networks. It also shows the use of IEEE compliant MACsec to encrypt and authenticate the link for security. As more and more critical applications and data migrate to the cloud, MACsec provides data encryption and authentication to preserve privacy. Such a solution is mandatory in front of a traditional DSP to provide a complete DCI solution.

Another demonstration showcases Xilinx's new 56G PAM-4 transceiver test chip in 16nm FinFET delivering optimized performance for backplane and LR applications.

http://www.xilinx.com

Friday, February 24, 2017

Xilinx Integrates RF analogue Tech into All Programmable MPSoCs

Xilinx has announced what it claims is a disruptive integration and architectural technique for 5G wireless with the addition of RF-class analogue technology into its 16 nm All Programmable MPSoC products.

Xilinx's new All Programmable RFSoCs eliminate the need for discrete data converters, providing a claimed 50-75% reduction in terms of power and footprint for 5G massive MIMO and millimetre-wave (mmWave) wireless backhaul applications.

The company noted that large scale 2D antenna arrays will be a key element for increasing spectral efficiency and network densification for 5G networks. The integration of ADCs and DACs into Xilinx's All Programmable SoC devices is designed to enable radio and wireless backhaul units to meet previously unattainable power and form factor demands, while also allowing higher channel density.

In addition, the new RFSoC devices can also help manufacturers streamline design and development cycles and meet 5G deployment timelines.

Xilinx's new All Programmable RFSoC devices offer features including:

1. Direct RF sampling to simplify analogue design and enhance accuracy and enable a smaller form factor and lower power consumption.

2. 12-bit ADCs supporting up to 4 GS/s, high channel count, with digital down-conversion.

3. 14-bit DACs supporting up to 6.4 GS/s, high channel count and digital up conversion.

The new RFSoC integrated subsystem specifically targets a range of applications including high bandwidth remote radio and backhaul systems for 5G deployments and remote node architectures (R-PHY) for DOCSIS 3.1 cable broadband systems.


Monday, May 23, 2016

Xilinx Adds Data Center Accelerators to 16nm UltraScale+ Roadmap

Xilinx plans to add acceleration enhanced technologies for the Data Center to its 16nm UltraScale+ product roadmap.

The resulting products will deliver the combination of Xilinx's 16nm FinFET+ FPGAs with integrated High-Bandwidth Memory (HBM), and support for the recently announced Cache Coherent Interconnect for Acceleration technology (CCIX).

CCIX is initially driven by a group of seven companies to enable an acceleration framework that works with multiple processor architectures.

Specifically, Xilinx HBM-enabled FPGAs will improve acceleration capabilities by offering 10X higher memory bandwidth relative to discrete memory channels. HBM technology enables multi-terabit memory bandwidth integrated in package for the lowest possible latency.

"Having already delivered 19 billion transistors on a chip at 20nm leveraging our second generation 3D IC technology, we are creating a third generation 3D IC breakthrough  for data center acceleration and other compute intensive designs," said Victor Peng, executive vice president and general manager, Programmable Products at Xilinx. "When combined with next generation CCIX acceleration framework and our software defined SDAccel™  development environment, this technology will enable a new breed of high-density, flexible platforms for accelerating compute, storage and networking applications."

http://www.xilinx.com

Saturday, March 12, 2016

Xilinx Develops 56G PAM4 Transceiver Technology

Xilinx has developed a 16nm FinFET+-based programmable device running 56G transceiver technology using the 4-level Pulse Amplitude Modulation (PAM4) transmission scheme.

Xilinx said PAM4 solutions will help drive the next wave of Ethernet deployment for optical and copper interconnects by doubling bandwidth on the existing infrastructure.

"Our customers are already anticipating how to accelerate their next generation applications. We recognize the need to raise awareness of 56G PAM4 technology solutions now, to help prepare them to transition their own designs," said Ken Chang, vice president of the SerDes technology group at Xilinx. "I am delighted to be able to showcase our technology."

http://www.xilinx.com

Friday, February 5, 2016

Xilinx FPGA to Support 25G per Lane Copper Cabling at Five Meters

Xilinx announced that its Virtex UltraScale FPGAs have achieved compliance to the 25GE, 50GE and 100GE copper cable and backplane IEEE and related specifications, which supports up to five meters of copper cabling in the data center and up to one meter of backplane interconnect.

These specifications include the IEEE 802.3bj 100GBASE-CR4/KR4, IEEE 802.3by 25GBASE-CR/CR-S/KR/KR-S, and 25 Gigabit Ethernet Consortium 50GBASE-CR2/KR2. Data center customers can now leverage nx25G lanes of copper cabling versus optics for more cost and power-optimized solutions to connect servers to top-of-rack switches using any off-the-shelf, specification-compliant vendor.

"With Virtex UltraScale FPGAs in volume production, and as the industry's only FPGA supplier compliant to the 25Gb per lane copper cable and backplane specifications, we are committed to helping our customers utilize the lowest risk and most cost effective solutions for their data centers," said Kirk Saban, senior director of FPGA and SoC product management and marketing.

http://press.xilinx.com/2016-02-02-Xilinx-Transceiver-Breakthrough-Brings-Greater-Cost-Efficiency-to-Data-Center-Interconnects

Xilinx Tech Ventures to Invest in Cloud & NFV Start-ups

Xilinx Technology Ventures is launching a Data Center Ecosystem Investment Program that will focus primarily on technologies that expand Xilinx's data center products and offerings and ignite industry innovation, time to market advantage, and lower overall cost of ownership. The new program targets solutions for emerging workload applications such as machine learning, image and video processing, data analytics, storage data base acceleration, and network acceleration.

As part of this program, Xilinx recently completed its first data center ecosystem investment in TeraDeep, Inc., a company specializing in convolutional neural networks-based machine learning. TeraDeep is widely recognized for its state-of-the-art deep learning expertise and acceleration technology which runs on Xilinx® FPGAs. Through this investment, TeraDeep will continue to work closely with Xilinx to further optimize its solutions on Xilinx-based FPGA boards.

"Through this investment program, we want to help enable start-ups that create libraries, middleware, and application software to accelerate the broad deployment of Xilinx FPGA solutions in the Data Center," said Greer Person, senior director, Corporate Business Development. "In addition to funding, our portfolio companies often gain access to Xilinx business and technology experts, products, and design environments to help them create more competitive solutions, accelerate time-to-market, and reduce development costs."

http://www.xilinx.com/about/technology-investments.html

Sunday, January 31, 2016

Xilinx Ships 16nm Virtex UltraScale+ FinFET FPGAs

Xilinx announced first customer shipment of its Virtex UltraScale+ FPGA, the industry's first high-end FinFET FPGA built using TSMC's 16FF+ process.

The Virtex UltraScale+ devices join the Zynq UltraScale+ MPSoCs and Kintex UltraScale+ FPGAs showcasing the availability of all three families of the Xilinx 16nm portfolio. The UltraScale+ portfolio provides 2 – 5x greater system-level performance/watt over 28nm devices and is suited for LTE Advanced and early 5G Wireless, Automotive ADAS, Cloud Computing, Industrial Internet-of-Things (IoT), SDN/NFV, and Video/Vision markets.      

Xilinx said it is actively engaged with more than one hundred customers on the UltraScale+ portfolio with design tools, and has already shipped devices and/or boards to over sixty of these customers.

"The successful delivery of our Virtex UltraScale+ FPGA marks the availability of all three UltraScale+ 16nm families, which are already providing more than one hundred customers with the ability to develop next generation designs using cutting edge FinFET-based devices, development boards and tools. Our "Three-Peat" execution – with three consecutive generations of leadership technology at 28nm, 20nm, and now at 16nm – showcases our sustained commitment to being first to market with the most advanced products in our industry," said Victor Peng, executive vice president and general manager of the Programmable Products Group at Xilinx.

http://www.xilinx.com

Xilinx Outlines its 16nm UltraScale+ Family of FPGAs

Xilinx introduced its next-generation 16nm UltraScale+ family of FPGAs, featuring new memory, 3D-on-3D and multi-processing SoC (MPSoC) technologies.

The UltraScale+ family also includes a new interconnect optimization technology and will leverage TSMC's 16FF+ FinFET 3D transistors.

Xilinx estimates the UltraScale+ family will deliver 2–5X greater system level performance/watt over 28nm devices. Key applications are expected to include LTE Advanced and early 5G wireless, terabit wired communications, automotive ADAS, and industrial Internet-of-Things (IoT).

Some highlights:

  • Memory Enhanced Programmable Devices: UltraRAM attacks one of the largest bottlenecks affecting FPGA- and SoC-based system performance and power by enabling SRAM integration. The new on-chip memory could be used for deep packet and video buffering. UltraRAM scales up to 432 Mbits in a variety of configurations.
  • SmartConnect Technology: Interconnect optimization technology for FPGAs. It provides additional 20-30 percent performance, area, and power advantages through intelligent system-wide interconnect optimization. While the UltraScale architecture attacks the silicon-level interconnect bottleneck through re-architected routing, clocking, and logic fabric, SmartConnect applies interconnect topology optimizations to match design-specific throughput and latency requirements while reducing interconnect logic area. 
  • 3D-on-3D Technology: The high end of the UltraScale+ portfolio leverages the combined power of 3D transistors and third generation of Xilinx 3D ICs. Just as FinFETs enable a non-linear improvement in performance/watt over planar transistors, 3D ICs enable a non-linear improvement in systems integration and bandwidth/watt over monolithic devices.   
  • Heterogeneous Multi-processing Technology: The new Zynq UltraScale+ MPSoCs include all of the aforementioned FPGA technologies with an unprecedented level of heterogeneous multi-processing, deploying the "the right engines for the right tasks." These new devices deliver approximately 5X system level performance/watt relative to previous alternatives.  At the center of the processing-subsystem is the 64-bit quad-core ARM® Cortex®-A53 processor, capable of hardware virtualization, asymmetric processing, and full ARM TrustZone® technology support.

"Xilinx is delivering a generation ahead of value with 16nm FinFET FPGAs and MPSoCs to a variety of next generation applications," said Victor Peng, executive vice president and general manager of the Programmable Products Group at Xilinx.  "Our new UltraScale+ 16nm portfolio delivers 2-5X higher system performance-per-watt, a dramatic leap in system integration and intelligence, and the highest level of security and safety required by our customers. These capabilities enable Xilinx to significantly expand its available market."

Early customer engagements are in process for the UltraScale+ families. First tape out and early access release of the design tools are scheduled for the second calendar quarter of 2015.

http://www.xilinx.com/products/technology/ultrascale.html

Thursday, October 8, 2015

Qualcomm Samples 24-core Server Chip based on ARMv8-A

Qualcomm has begun sampling a 24-core SoC based on the ARMv8-A instruction set and built using advanced FinFet technology.  The company's Server Development Platform (SDP) is aimed at high-density data centers.

Qualcomm also announced two key partnerships.  The company is partnering with Xilinx to deliver heterogeneous computing solutions for data centers with Qualcomm’s server processor and Xilinx FPGAs. Qualcomm is partnering with Mellanox to enable advanced, cost effective platforms for servers and storage that deliver the fastest, most efficient interconnect solutions for data transfer and analysis with Qualcomm’s server CPU and Mellanox’s Ethernet and InfiniBand interconnect solutions.

"The release of our evaluation system is a major milestone for Qualcomm Technologies. As data centers evolve to support the exponential growth and innovation in data, connectivity and cloud services, Qualcomm Technologies is creating an ecosystem to meet the needs of these next-generation data centers with Qualcomm-based server technologies. Our customers are eager to test and evaluate our Server Development Platform and begin porting their software. We are incorporating their feedback into our product offering with the goal of ensuring system and software readiness by the time we are in full production,” stated Anand Chandrasekher, senior vice president, Qualcomm Technologies.

http://www.qualcomm.com

Tuesday, July 7, 2015

Xilinx Collaborates with China Mobile on 5G Fronthaul Interface

Xilinx is working with China Mobile Research Institute (CMRI) for the development of the next generation fronthaul interface (NGFI) for 5G. Fronthaul is the link between the baseband and radio units, which are expected to be distributed in 5G architectures.

Specifically, Xilinx is contributing to the NGFI eco-system with a validated NGFI reference design on its Zynq SoC platform. The reference design, which can easily be migrated to other Zynq and Zynq UltraScale+ MPSoC devices, will serve as a baseline framework for 4.5G/5G wireless network research.

"It's time to rethink current fronthaul solutions and addressing the major challenges for CRAN deployment is critical," said Dr. Chih-Lin I, chief scientist of China Mobile Research Institute. "New efficient and flexible fronthaul solutions are being worked on for the enablement of large scale CRAN deployment and our work with Xilinx will surely accelerate the delivery of such solutions."

"Current 'hard' mobile networks are plagued with a number of serious challenges including time to market, service innovation, energy efficiency, TCO and interoperability," said Sunil Kar, vice president of wireless communications at Xilinx. "Through our close collaboration with China Mobile Research Institute, we are working to address these challenges and identify the key technologies and components for highly optimized next generation fronthaul interfaces."

http://labs.chinamobile.com/cran/wp-content/uploads/White%20Paper%20of%20Next%20Generation%20Fronthaul%20Interface.PDF
http//www.xilinx.com

Sunday, March 22, 2015

Xilinx Releases 100G 802.3bj Reed-Solomon FEC

Xilinx has begun shipping its 100G IEEE 802.3bj Reed-Solomon FEC (RS-FEC) IP for data center, service provider, and enterprise applications.

The 100G RS-FEC LogiCORE IP solution seamlessly connects to Xilinx's integrated or soft 100G Ethernet MAC IP running on Virtex® UltraScale, enabling emerging optical solutions such as SR4, CWDM4, PSM4 or ER4f.

Xilinx is the first to demonstrate a complete 100G RS-FEC IP solution with Finisar and TE Connectivity (TE) optics showcased in multiple demonstrations at OFC 2015,

http://www.xilinx.com/esp/wired/wired_ip_resources.htm#connectivity

See also