Showing posts with label TSMC. Show all posts
Showing posts with label TSMC. Show all posts

Monday, April 22, 2019

Cadence says ready for TSMC’s 5nm FinFET

Cadence Design Systems confirmed that its digital, signoff and custom/analog tools have been certified for Design Rule Manual (DRM) and SPICE v1.0, and Cadence IP has been enabled for the TSMC 5nm process. The corresponding process design kits (PDKs) featuring integrated tools, flows and methodologies are now available for traditional and cloud-based environments. Additionally, mutual customers have already completed several tapeouts using Cadence tools, flows and IP for full production development on the TSMC 5nm process technology.

Cadence said it has delivered a fully integrated digital implementation and signoff tool flow, which has been certified on TSMC’s 5nm process that has the benefits of process simplification provided by extreme ultraviolet (EUV) lithography. The Cadence full-flow includes the Innovus Implementation System, Liberate Characterization Portfolio, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Pegasus™ Verification System.

“We’re continuing to broaden our collaboration with TSMC to facilitate 5nm FinFET adoption, giving customers access to the latest tools and IP for advanced process design creation,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Our R&D team has focused heavily on developing new features and performance improvements so that our digital and signoff and custom/analog tools and IP can be used with complete confidence, enabling customers to achieve first-pass silicon success and deliver end products within aggressive time-to-market schedules.”

http://www.cadence.com/go/tsmc5nmca


Thursday, April 11, 2019

TSMC gets ready for the arrival of 5 nanometer

TSMC has delivered a complete version of its 5 nanometer (nm) design infrastructure to design partners.

TSMC said its kit enables 5nm systems-on-chip (SoC) designs in next-generation advanced mobile and high-performance computing (HPC) applications, especially for 5G and AI.

“TSMC’s 5-nanometer technology offers our customers the industry’s most advanced logic process to address the exponentially growing demand for computing power driven by AI and 5G,” said Cliff Hou, Vice President of Research & Development/Technology Development at TSMC. “5-nanometer technology requires deeper design-technology co-optimization. Therefore, we collaborate seamlessly with our ecosystem partners to ensure we deliver silicon-validated IP blocks and EDA tools ready for customer use. As always, we are committed to helping customers achieve first-time silicon success and faster time-to-market.”

TSMC’s 5nm process is already in risk production and offers IC designers a new level of performance and power optimization targeted at the next generation of high-end mobile and HPC applications.

http://www.tsmc.com

Sunday, August 5, 2018

TSMC's fabs disrupted by virus, some shipments will be delayed

TSMC was disrupted by a computer virus outbreak on the evening of August 3 that affected a number of computer systems and fab tools in Taiwan.

As of Sunday at 14:00 Taiwan time, TSMC stated that about 80% of its impacted tools have been recovered, and the company expects full recovery on August 6.

TSMC expects this incident to cause shipment delays and additional costs. The company stated:

"We estimate the impact to third quarter revenue to be about three percent, and impact to gross margin to be about one percentage point. The Company is confident shipments delayed in third quarter will be recovered in the fourth quarter 2018, and maintains its forecast of high single-digit revenue growth for 2018 in U.S. dollars given on July 19, 2018."

TSMC also noted that data integrity and confidential information was not compromised.



Thursday, May 19, 2016

ARM Announces First Multicore Test Chip Based on TSMC's 10FinFET

ARM announced the first multicore, 64-bit ARM v8-A processor test chip based on TSMC’s 10FinFET process technology.

ARM cited significant power and efficiency gains relative to TSMC’s 16FinFET+ process technology.

“Efficiency is a primary guiding principle in SoC design for premium mobile applications due to increasing demands on device performance,” said Pete Hutton, executive vice president and president of product groups, ARM. “TSMC’s 16FFLL+ process and ARM Cortex® processors have already set new standards for efficiency. Our collaboration with TSMC on 10FinFET ensures SoC-wide efficiency that will allow our silicon partners even greater room to innovate while staying within strict power budgets.”

“Our partnership with ARM offers our ecosystem rapid advances in process and IP and accelerates customer product development cycles,” said Dr. Cliff Hou, vice president, R&D, TSMC. “Together, we are defining processor technologies that continue to propel the mobile market. Our latest endeavor, enabling ARM processors on TSMC 10FinFET technology, is transformative for the end user experience across premium mobile and a diverse range of consumer electronic goods.”

http://www.arm.com

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