Showing posts with label TSMC. Show all posts
Showing posts with label TSMC. Show all posts

Wednesday, June 2, 2021

TSMC advances its 3DFabric chip stacking technologies

TSMC cited progress with its "3DFabric" advanced packaging and chip stacking technologies at the company’s online 2021 Technology Symposium. 

TSMC will be offering larger reticle-size for both its InFO_oS and CoWoS® packaging solutions in 2021, enabling larger floor plans for chiplet and high-bandwidth memory integration. Additionally, the chip-on-wafer (CoW) version of TSMC-SoIC will be qualified on N7-on-N7 this year with production targeted for 2022 at a new fully-automated factory.



In addition, TSMC is introducing its N5A process node, the newest member of the 5nm family and aimed at satisfying the growing demand for computing power in newer and more intensive automotive applications such as AI-enabled driver assistance and the digitization of vehicle cockpits.

TSMC also said its N3 process node technology is poised to begin volume production in the second half of 2022.

https://pr.tsmc.com/english/news/2831

Sunday, April 11, 2021

Achronix samples 7nm Speedster FPGA

Achronix announced sampling of its 7nm Speedster 7t AC7t1500 FPGAs to customers ahead of schedule. 

The Speedster7t family targets high bandwidth workloads in AI/ML, 5G infrastructure, networking, computational storage, and test/measurement.

Achronix is leveraging TSMC's 7nm process technology.

The AC7t1500 has been optimized for high bandwidth applications and includes the industry's first 2D network-on-chip (NoC) with more than 20 Tbps of bi-directional bandwidth, 112 Gbps SerDes, PCIe Gen5, 400G Ethernet and 4 Tbps external memory bandwidth with its GDDR6 memory interfaces. The 2D NoC has dedicated high-bandwidth paths across the entire FPGA fabric interconnecting all functional blocks and peripheral I/O to each other and to the FPGA fabric. The 2D NoC eliminates complex routing bottlenecks found in traditional FPGAs and can transmit or receive 512Gbps at each of the 80 nodes across the FPGA yielding greater than 20Tbps of bidirectional bandwidth. The company says this structure simplifies routing and accelerates timing closure, allowing designers to use the available logic and memory resources to create differentiation in their designs. 

The new FPGAs also include an array of the new innovative machine learning processors (MLPs) which are ideally suited for the diverse and high-performance workloads required in AI/ML applications. The Speedster7t FPGAs are supported by the Achronix tool suite which includes Synplify Pro synthesis and the ACE place, route, and timing tools. 

https://www.achronix.com/

Engineering samples of the AC7t1500 FPGAs are shipping to customers today. Achronix expects to complete full device validation of the FPGA fabric, hard IP and peripheral interfaces in the second half of 2021 and will begin shipping production devices by the end of 2021.

  • In January 2021, Achronix entered into a definitive merger agreement with ACE Convergence Acquisition Corp. (Nasdaq: ACEV) in a transaction that would result in Achronix being listed on Nasdaq. The transaction is expected to close in the first half of 2021.

Friday, May 15, 2020

TSMC to invest $12 billion in 5nm fab in Arizona

TSMC confirmed plans to build and operate an advanced semiconductor fab in Arizona -- its secend manufacturing site in the United States. The company already operates a fab in Camas, Washington and design centers in Austin and San Jose.

The new facility in Arizona represents a $12 billion investment. It will utilize TSMC’s 5-nanometer technology for semiconductor wafer fabrication, have a 20,000 semiconductor wafer per month capacity.

TSMC said the fabrication facility will create over 1,600 high-tech professional jobs directly, and thousands of indirect jobs in the semiconductor ecosystem. Construction is planned to start in 2021 with production targeted to begin in 2024.

TSMC cited a strong partnership with the U.S. administration and the State of Arizona on this project.

https://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&newsid=THGOANPGTH


  • TSMC is expected to ramp 5nm production in Taiwan beginning in Q2

  • TSMC's 2020 current production capacity is approximately 12 million wafers

Monday, April 22, 2019

Cadence says ready for TSMC’s 5nm FinFET

Cadence Design Systems confirmed that its digital, signoff and custom/analog tools have been certified for Design Rule Manual (DRM) and SPICE v1.0, and Cadence IP has been enabled for the TSMC 5nm process. The corresponding process design kits (PDKs) featuring integrated tools, flows and methodologies are now available for traditional and cloud-based environments. Additionally, mutual customers have already completed several tapeouts using Cadence tools, flows and IP for full production development on the TSMC 5nm process technology.

Cadence said it has delivered a fully integrated digital implementation and signoff tool flow, which has been certified on TSMC’s 5nm process that has the benefits of process simplification provided by extreme ultraviolet (EUV) lithography. The Cadence full-flow includes the Innovus Implementation System, Liberate Characterization Portfolio, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Pegasus™ Verification System.

“We’re continuing to broaden our collaboration with TSMC to facilitate 5nm FinFET adoption, giving customers access to the latest tools and IP for advanced process design creation,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Our R&D team has focused heavily on developing new features and performance improvements so that our digital and signoff and custom/analog tools and IP can be used with complete confidence, enabling customers to achieve first-pass silicon success and deliver end products within aggressive time-to-market schedules.”

http://www.cadence.com/go/tsmc5nmca


Thursday, April 11, 2019

TSMC gets ready for the arrival of 5 nanometer

TSMC has delivered a complete version of its 5 nanometer (nm) design infrastructure to design partners.

TSMC said its kit enables 5nm systems-on-chip (SoC) designs in next-generation advanced mobile and high-performance computing (HPC) applications, especially for 5G and AI.

“TSMC’s 5-nanometer technology offers our customers the industry’s most advanced logic process to address the exponentially growing demand for computing power driven by AI and 5G,” said Cliff Hou, Vice President of Research & Development/Technology Development at TSMC. “5-nanometer technology requires deeper design-technology co-optimization. Therefore, we collaborate seamlessly with our ecosystem partners to ensure we deliver silicon-validated IP blocks and EDA tools ready for customer use. As always, we are committed to helping customers achieve first-time silicon success and faster time-to-market.”

TSMC’s 5nm process is already in risk production and offers IC designers a new level of performance and power optimization targeted at the next generation of high-end mobile and HPC applications.

http://www.tsmc.com

Sunday, August 5, 2018

TSMC's fabs disrupted by virus, some shipments will be delayed

TSMC was disrupted by a computer virus outbreak on the evening of August 3 that affected a number of computer systems and fab tools in Taiwan.

As of Sunday at 14:00 Taiwan time, TSMC stated that about 80% of its impacted tools have been recovered, and the company expects full recovery on August 6.

TSMC expects this incident to cause shipment delays and additional costs. The company stated:

"We estimate the impact to third quarter revenue to be about three percent, and impact to gross margin to be about one percentage point. The Company is confident shipments delayed in third quarter will be recovered in the fourth quarter 2018, and maintains its forecast of high single-digit revenue growth for 2018 in U.S. dollars given on July 19, 2018."

TSMC also noted that data integrity and confidential information was not compromised.



Thursday, May 19, 2016

ARM Announces First Multicore Test Chip Based on TSMC's 10FinFET

ARM announced the first multicore, 64-bit ARM v8-A processor test chip based on TSMC’s 10FinFET process technology.

ARM cited significant power and efficiency gains relative to TSMC’s 16FinFET+ process technology.

“Efficiency is a primary guiding principle in SoC design for premium mobile applications due to increasing demands on device performance,” said Pete Hutton, executive vice president and president of product groups, ARM. “TSMC’s 16FFLL+ process and ARM Cortex® processors have already set new standards for efficiency. Our collaboration with TSMC on 10FinFET ensures SoC-wide efficiency that will allow our silicon partners even greater room to innovate while staying within strict power budgets.”

“Our partnership with ARM offers our ecosystem rapid advances in process and IP and accelerates customer product development cycles,” said Dr. Cliff Hou, vice president, R&D, TSMC. “Together, we are defining processor technologies that continue to propel the mobile market. Our latest endeavor, enabling ARM processors on TSMC 10FinFET technology, is transformative for the end user experience across premium mobile and a diverse range of consumer electronic goods.”

http://www.arm.com