Showing posts with label Synopsys. Show all posts
Showing posts with label Synopsys. Show all posts

Tuesday, March 23, 2021

Synopsys announces PCIe 6.0 solutions

Synopsys introduced its intellectual property solution for PCI Express (PCIe) 6.0 technology that includes controller, PHY and verification IP.

The solutions enables early development of PCIe 6.0 system-on-chip (SoC) designs. 

Synopsys' DesignWare IP for PCIe 6.0 supports the latest features in the standard specification including, 64 GT/s PAM-4 signaling, FLIT mode and L0p power state. To achieve the lowest latency with maximum throughput for all transfer sizes, the DesignWare Controller for PCI Express 6.0 utilizes a MultiStream architecture, delivering up to 2X the performance of a single-stream design. The Controller, with available 1024-bit architecture, allows designers to achieve 64 GT/s x16 bandwidth while closing timing at 1GHz. In addition, the controller provides optimal flow with multiple data sources and in multi-virtual channel implementations. To facilitate accelerated testbench development with built-in verification plan, sequences and functional coverage, the VC Verification IP for PCIe uses native SystemVerilog/UVM architecture that can be integrated, configured and customized with minimal effort.

"Advanced cloud computing, storage and machine learning applications are transferring significant amounts of data, requiring designers to incorporate the latest high-speed interfaces with minimal latency to meet the bandwidth demands of these systems," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. "With Synopsys' complete DesignWare IP solution for PCI Express 6.0, companies can get an early start on their PCIe 6.0-based designs and leverage Synopsys' proven expertise and established leadership in PCI Express to accelerate their path to silicon success."

The DesignWare Controller and PHY IP for PCIe 6.0 early access are scheduled to be available in Q3 of 2021. The Verification IP for PCIe 6.0 is available now. 

https://www.synopsys.com/designware-ip/interface-ip/pci-express/pci-express-6.html

Tuesday, March 16, 2021

Rockley employs Synopsys for its silicon photonics designs

Rockley Photonics has adopted Synopsys solutions to accelerate the design and verification of silicon photonics for sensing and datacom applications. 

Specifically, Rockley is using tools from Synopsys' Photonic Solutions platform, including OptoCompiler, OptoDesigner, OptSim Circuit, RSoft Photonic Device Tools and IC Validator. Rockley plans to use Synopsys solutions to design and optimize photonic devices, create process design kits (PDKs) and tape out photonic ICs.

Rockley was an early adopter of Synopsys' OptoCompiler tool following its commercial launch in September 2020. OptoCompiler is the industry's first unified electronic and photonic design platform, combining mature and dedicated photonic technology with Synopsys' industry-proven custom and analog-mixed signal tools to enable engineers to produce and verify complex photonic IC designs quickly and accurately.

"Rockley's unique photonic chipset technology with silicon photonics at its core is driving the growth of integrated optical components in healthcare, machine vision and data communications," said Andrew Rickman, chief executive at Rockley. "The PDA platform Rockley has created by utilizing OptoCompiler allows our engineers to define, simulate, lay out and verify Photonic ICs quickly and efficiently to meet our quality and schedule goals. Synopsys' technical support has been instrumental in ensuring Rockley met its tape-out goals. We look forward to additional efficiency gains by expanding our use of Synopsys' Photonic Solutions tools."

https://www.synopsys.com/

Rockley Photonics secures $50 million in funding

 Rockley Photonics, a start-up specializing in integrated optical chips and modules, has closed an additional $50 million of growth funding from leading deep-tech VCs, strategic investors, and institutional funds including Credit Suisse backed SIG-i Capital and Applied Ventures, the venture capital arm of Applied Materials, as well as existing shareholders. To date, Rockley has raised over $225 million of financing to develop its unique silicon photonics platform.

“It is testament to the strength of our technology and emerging market opportunities that we have attracted such a preeminent list of new investors to join many of our existing shareholders in this funding round,” said Andrew Rickman, chief executive officer, Rockley Photonics. “This round provides the funding for Rockley as it moves into the next exciting growth phase and develops next generation disruptive silicon photonics powered healthcare and wellness sensors and communications products for its Tier-1 customers.”

Rockley Photonics was founded by Dr. Andrew Rickman in 2013. The company has offices in Pasadena, San Jose, Oxford, Cardiff, Cork, and Helsinki.

Thursday, September 27, 2018

ECOC 2018: Synopsys and SMART Photonics announce InP kit

At ECOC 2018, Synopsys and SMART Photonics, which is a European manufacturer of InP Photonics components with production and research facilities located in Eindhoven, The Netherlands, introduced a production-ready process design kit (PDK) based on SMART Photonics' Indium Phosphide (InP) process.

Synopsys said its PIC Design Suite, which comprises OptSim Circuit and OptoDesigner tools, provides a seamless PIC design flow from idea to manufacturing from a single solutions provider. The addition of the SMART PDK to OptSim Circuit, combined with the PDK's availability in OptoDesigner, enables users to use the PIC Design Suite to schematically capture and simulate InP-based PIC designs with the SMART PDK building blocks, and then synthesize and verify a SMART-foundry-compatible layout.

"This is another example of a world-class PIC foundry taking advantage of the new opportunities offered by rapid advances in photonic integration," said Tom Walker, group director of R&D for Synopsys' Photonic Solutions. "We are excited to be working with SMART Photonics and to be able to give our mutual customers the ability to design advanced custom photonic applications using the SMART Photonics InP semiconductor process."

http://www.synopsys.com

Tuesday, May 30, 2017

Synopsys unveils DesignWare multi-protocol 25 Gbit/s PHY IP

Synopsys, describing itself as the Silicon to Software partner for companies developing electronic products and software applications, announced its new DesignWare Multi-Protocol 25 Gbit/s PHY IP targeting high-performance computing applications including machine learning and artificial intelligence.

Synopsys' new PHY IP allows designers to integrate multiple protocols including PCI Express 4.0, 25 Gigabit Ethernet, SATA and CCIX into system-on-chips (SoCs) targeting the 7 nm and 16 nm FinFET processes. The multi-protocol 25 Gbit/s PHY is claimed to reduce power and area requirements by over 35% compared to the 16 Gbit/s PHY solution via optional power management features such as I/O supply under drive and decision feedback equalisation (DFE) bypass.

In addition, the solutions features programmable continuous calibration and adoption (CCA), which is designed to optimise performance across voltage and temperature variations, which is key for applications in harsh data centre environments.

Designers are able to integrate the multi-protocol 25 Gbit/s PHY with Synopsys' digital controllers and verification IP to provide a complete, low latency IP solution that is compliant with the industry-standard protocol specifications.

The new DesignWare multi-protocol 25 Gbit/s PHY IP offers designers key features including:

1.         Flexible clock multiplier unit (CMU) with dual PLLs and dividers to support flexible multi-protocol configurations while transmitting data across lossy channels.

2.         Analogue front-end that incorporates adaptive continuous time linear equaliser (CTLE), decision feedback equalisation (DFE) and feed forward equalisation (FFE) for enhanced signal integrity and jitter performance.

3.         Embedded bit error rate (BER) circuitry for evaluating channel quality and on-die test features for testability and visibility into system performance without the need for external test equipment.

Synopsys noted that the silicon design kit for DesignWare multi-protocol 25 Gbit/s PHY IP for TSMC 7 nm FinFET process is currently available; the silicon design kit for TSMC's 16 nm FinFET process is scheduled to be available in October.


The Synopsys DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analogue IP, wired and wireless interface IP, security IP, embedded processors and subsystems.


Tuesday, March 28, 2017

Synopsys Upgrades RSoft Photonic Component Suite

Synopsys, a global developer of software, IP and services for the development of chips and electronic systems, announced the latest release of its RSoft Photonic Component Design Suite software for the design of photonic devices and components used in optical communications, optoelectronics and semiconductor manufacturing.

The latest version 2017.03 of the RSoft design suite is intended to speed optoelectronic device analysis via an updated interface to Synopsys' Sentaurus TCAD products and new general monitor objects within the RSoft BeamPROP tool that help speed simulations of waveguide photodetectors by up to a claimed 100x compared to finite-difference-time-domain (FDTD) methods.

The release also expands the RSoft tools' capabilities for modelling nanoscale optical structures with an improved bi-directional scattering distribution function (BSDF) calculation for mixed-level LED/OLED simulations.

Further enhancement include new discrete multi-tone (DMT) modulation format functions in the OptSim tool for modelling and simulating DMT-based data links, including access networks and 100/400 Gigabit Ethernet-based data centre links, and a ModeSYS tool update for the design and analysis of large-core multimode fibre systems.

The enhanced Sentaurus TCAD interface is designed to enable integration of the RSoft optical tools in Sentaurus Workbench for in-depth, multidisciplinary simulations of optoelectronic devices. Additional improvements include support for systems with dispersive materials and dynamic updates of materials and the common simulation area.

Native bi-directional data interchange between RSoft tools and Sentaurus Workbench has been expanded to include the BeamPROP tool for waveguide detector simulation to speed designs. Specifically, new general monitor objects of BeamPROP perform efficient optical power absorption calculations to speed photodetector simulations by up to 100x versus FDTD-based methods, enabling faster device characterisation and optimisation.

The new release also enhances Synopsys' LightTools and the RSoft mixed-level co-simulation method, which combines ray- and wave-based techniques to enable efficient incorporation of polarised diffraction effects in LightTools' ray-tracing simulator. The co-simulation method employs the RSoft BSDF capability, which now performs improved scattering calculations of polarisation-dependent effects in nanoscale optical structures for the design of LEDs and OLEDs.

https://www.synopsys.com/