Showing posts with label Silicon. Show all posts
Showing posts with label Silicon. Show all posts

Monday, December 14, 2020

NEC spins out NanoBridge Semiconductor

 NanoBridge Semiconductor, a start-up based in Tsukuba, Japan, issued series A preferred stock to Japan Industrial Partners, Inc., NEC Corporation (NEC; TSE: 6701), and other companies to raise approximately 130 million yen.

NanoBridge was established by NEC researchers in September 2019 to commercialize a technology to control the creation or destruction of nanometer sized metal bridges in a solid electrolyte through the application of voltage, thereby realizing on and off-switch status.  NanoBridge does not require power to maintain an on or off status, and is highly resistant to both radiation and extreme temperatures. NEC has transferred related intellectual property to the new spin-out company.

Potential applications for the nanobridge technology include FPGAs and memories that repeatedly rewrite circuits. 

"The discovery of the atomic switch, based on the movement of atoms rather than electrons, was a major breakthrough in basic science," said Richard E. Dyck, Director, Japan Industrial Partners, Inc. "The team at NanoBridge, after two decades of skilled and focused engineering, has transformed this breakthrough into the realm of practical application. It is exciting to see the NanoBridge atomic switch can now be manufactured economically and in volume, on standard production equipment."

https://nanobridgesemi.com/

Sunday, December 13, 2020

Xsight Labs samples 25.6T data center switch chip with 100G SerDes

Xsight Labs, a fabless semiconductor start-up based in Israel, emerged from stealth to announce sampling of a 25.6T 32 x 800G data center switch and a 12.8T 32 x 400G data center switch based on 100G PAM4 SerDes.

The company's X1 switch chip, which is now sampling to alpha customers, is fabricated in 7nm silicon. 

Some highlights: 

  • The X1 chip operates at less than 300W for 25.6T and under 200W for 12.8T (for typical data center use cases)
  • Built with256 x 100G LR PAM4 SerDes, X1 enables retimer-less design, supporting in-rack DAC connectivity for the 100G ecosystem. 
  • X1 supports the new 800G optics ecosystem, delivering a 2x improvement in port density vs. 400G optics.
  • X1 leverages a fully shared buffer architecture with wire speed in-cast performance for worst-case microburst absorption.
  • X1 supports an extensive suite of programmable Dataplane Telemetry that enables visibility into the network for monitoring, troubleshooting and real-time analysis and decision making.

Supports a broad range of switch configurations: 

  • 25.6T: 256 x 100G, 128 x 200G, 64 x 400G, 32 x 800G
  • 12.8T: 256 x 50G, 128 x 100G, 64 x 200G, 32 x 400G, 16 x 800G

“Xsight Labs is the first in the world to sample a monolithic 7nm switch silicon that is on the frontier of the 100G SerDes ecosystem,” said Erez Shaizaf, Xsight Labs’ Co-Founder and Switch General Manager. “It is a true testament to the caliber of engineering talent that we have been able to assemble and we, as a team, are extremely proud of our execution.”

“The X1 family architecture has been built from the ground up to incorporate a unique set of value-added features like Application Optimized Switching, X-PND™, and X-IQ™, enabling customers’ switch deployments to achieve optimized latency and power,” said Gal Malach, Co-Founder and Chief Technology Officer at Xsight Labs.

https://xsightlabs.com/

 

  • Xsight Labs was co-founded by Guy Koren (CEO), who previously was CTO of EZchip Technologies (acquired by Mellanox in 2016 for $811M); Erez Shaizaf (GM of Switch Product Line), who previously was Vice President of Silicon at Mellanox and Director of VLSI at EZchip Technologies and Freescale; and Gal Malach (CTO), who previously was previously was Lead Architect and Director of VLSI at Mellanox, through the EZchip Technologies acquisition, where he drove architecture definition and execution.

Tuesday, December 8, 2020

Marvell ships its next gen access and metro Ethernet switching silicon

Marvell is now shipping its latest generation Prestera DX 7300 series of Ethernet switches for 5G carrier access and metro networks. Significantly, the new switches incorporate accurate time-sensitive features, integrated MACsec and advanced processing functionality, and support for 400G coherent optics.

Key features of the Prestera DX 7300 series 

  • ITU-T G.8273.2 Class C PTP/SyncE, Time Sensitive Networking (802.1CM) compliance for precise 5G timing
  • Advanced security with secure boot and integrated 802.1ae 256b MACsec engines for Layer2 data encryption
  • Segment Routing (SRV6) for advanced traffic engineering and service chaining
  • Enhanced network telemetry and intelligence for actionable metadata exports
  • 56Gbps PAM4 SerDes supporting port speeds up to 400Gbps
  • Flexible I/O speeds 1G/2.5/5/10/25/50/100/400G

Marvell notes that to support the new RAN deployment models for radio access fronthaul applications, its Prestera DX 7300 family integrates highly accurate time synchronization, 802.1CM Time-Sensitive-Network (TSN) for fronthaul, network slicing and native eCPRI-aware processing. The switches are part of Marvell's open radio access network (open RAN) and virtualized radio access network (vRAN) platform solutions, also announced today.

The Prestera DX 7300 series of switches integrate 56Gbps SerDes, high-capacity MACsec and advanced processing that can be matched with pluggable 400G-ZR optical modules. This functionality enables system manufacturers to develop solutions for multi-access edge computing (MEC) and data center interconnect (DCI) applications that benefit from traffic efficiency, openness and the optimized cost structure of packet Ethernet networks.

"As 5G brings rigorous data protection and performance demands to the transport network, the infrastructure has to meet the requirements for secured communications at higher speeds and data rates to support emerging use cases," said Guy Azrad, general manager and senior vice president of Switching at Marvell. "Our newest Prestera family offers the most secured switching solution with the high-speed interfaces needed to fulfill 5G potential at the industry's lowest power and footprint available today."


Thursday, December 3, 2020

Broadcom samples 7nm 8x100G PAM4 PHYs

Broadcom announced first sampling of a new family of 7nm 800G PAM-4 PHY devices. The portfolio includes 800G optical PHY devices (BCM8780X) optimized for QSFP-DD800 and OSFP transceiver module applications and an 800G 8:8 retimer PHY device (BCM87360) designed for line card applications. 

Highlights:

BCM87800/BCM87802 – Ultra-low power 7nm 800G optical PHYs for transceiver modules

  • Monolithic integrated 112Gbps laser driver with direct-drive PAM-4 output capability for EML and Silicon Photonics
  • Industry-leading DSP performance and power efficiency 

BCM87360 – Industry’s first 7nm 800G 8:8 retimer PHY for line cards

  • High-performance PAM-4 SerDes @ host and line side with link training and auto-negotiation
  • Interoperable with Broadcom switch merchant silicon and ASIC
  • Compliant to IEEE and OIF standards

“Continuing Broadcom’s strategy of building best-in-class PHYs, the two new 8x100G PHY families being sampled today expands our industry-leading 7nm PAM4 product line,” said Lorenzo Longo, senior vice president and general manager of the Physical Layer Products Division at Broadcom. “Broadcom provides optimized solutions for a wide range of optical and line card applications at both 50G and 100G. No other company offers the same portfolio breadth with an equivalent level of investment and IP availability to enable the next level of network expansion.” 



Tuesday, December 1, 2020

Qualcomm's Snapdragon 888 brings 3rd gen 5G modem, 6th gen processor

Qualcomm previewed its new flagship - the Snapdragon 888 - featuring its 3rd generation X60 5G Modem-RF System with global band coverage and a 6th generation AI Engine operating at an astonishing 26 tera operations per second (TOPS).

The 5G modem operates in mmWave and sub-6 across all major bands worldwide, and it brings support for 5G carrier aggregation, global multi-SIM, stand alone, non-stand alone, and Dynamic Spectrum Sharing.

The new 6th generation Qualcomm AI Engine features completely re-engineered Qualcomm Hexagon processor that improves performance and power efficiency.

“Creating premium experiences takes a relentless focus on innovation. It takes long term commitment, even in the face of immense uncertainty,” said Cristiano Amon, president, Qualcomm Incorporated. “It takes an organization that’s focused on tomorrow, to continue to deliver the technologies that redefine premium experiences.”



https://www.qualcomm.com/news/releases/2020/12/01/qualcomm-redefines-premium-snapdragon-tech-summit-digital-2020


AWS to deploy Intel's Gaudi AI accelerators in EC2 instances

AWS will begin offering EC2 instances with up to eight of Intel's Habana Gaudi accelerators for machine learning workloads.

Gaudi accelerators are specifically designed for training deep learning models for workloads that include natural language processing, object detection and machine learning training, classification, recommendation and personalization.

“We are proud that AWS has chosen Habana Gaudi processors for its forthcoming EC2 training instances. The Habana team looks forward to our continued collaboration with AWS to deliver on a roadmap that will provide customers with continuity and advances over time,” states David Dahan, chief executive officer at Habana Labs, an Intel Company.

ntel acquires Habana Labs for $2 billion - AI chipset

Intel has acquired Habana Labs, an Israel-based developer of programmable deep learning accelerators for the data center, for approximately $2 billion.

Habana’s Gaudi AI Training Processor is currently sampling with select hyperscale customers. Large-node training systems based on Gaudi are expected to deliver up to a 4x increase in throughput versus systems built with the equivalent number of GPUs. Gaudi is designed for efficient and flexible system scale-up and scale-out.

Additionally, Habana’s Goya AI Inference Processor, which is commercially available, has demonstrated excellent inference performance including throughput and real-time latency in a highly competitive power envelope. Gaudi for training and Goya for inference offer a rich, easy-to-program development environment to help customers deploy and differentiate their solutions as AI workloads continue to evolve with growing demands on compute, memory and connectivity.

Habana will remain an independent business unit and will continue to be led by its current management team. Habana will report to Intel’s Data Platforms Group, home to Intel’s broad portfolio of data center class AI technologies.

“This acquisition advances our AI strategy, which is to provide customers with solutions to fit every performance need – from the intelligent edge to the data center,” said Navin Shenoy, executive vice president and general manager of the Data Platforms Group at Intel. “More specifically, Habana turbo-charges our AI offerings for the data center with a high-performance training processor family and a standards-based programming environment to address evolving AI workloads.”

Habana Labs chairman Avigdor Willenz will serve as a senior adviser to the business unit as well as to Intel Corporation after Intel’s purchase of Habana.

“We have been fortunate to get to know and collaborate with Intel given its investment in Habana, and we’re thrilled to be officially joining the team,” said David Dahan, CEO of Habana. “Intel has created a world-class AI team and capability. We are excited to partner with Intel to accelerate and scale our business. Together, we will deliver our customers more AI innovation, faster.”


Interview: Habana Labs targets AI processors



Habana Labs, a start-up based in Israel with offices in Silicon Valley, emerged from stealth to unveil its first AI processor. Habana's deep learning inference processor, named Goya, is >2 orders of magnitude better in throughput & power than commonly deployed CPUs, according to the company. The company will offer a PCIe 4.0 card that incorporates a single Goya HL-1000 processor and designed to accelerate various AI inferencing workloads,...



Monday, November 30, 2020

SK Telecom designs its own AI chip

SK Telecom unveiled its own artificial intelligence (AI) chip and announced plans to enter the AI semiconductor business.

The South Korean telecoms operator said its new "SAPEON X220" chip is optimized for processing large amounts of data in parallel. Its deep learning computation speed is 6.7 kilo-_frames per second, which is 1.5 times faster than that of Graphics Processing Units (GPUs) for inference that are being widely used by AI-service companies. At the same time, it uses 20% less power than GPU by consuming 60 watts of energy and is about half the price of a GPU.

SKT plans to use the chip for its own AI-powered services, including for voice recognition. The aim is to generate synergies by combining AI semiconductor chips and 5G edge cloud. 

SAPEON X220 will also be utilized by SKT’s affiliate companies. For instance, ADT Caps will apply the chip to enhance the performance of its AI-based video monitoring service named T View. In addition, SAPEON X220 will be applied to the cloud server of the next-generation media platform of Cast.era, a joint venture of SKT and Sinclair Broadcast Group.

SKT also announced a plan to enter the AI as a Service (AIaaS) business. It will offer a complete solution package as a service by combining its AI chip and AI software, including diverse AI algorithms for features like content recommendation, voice recognition, video recognition and media upscaling, along with Application Programming Interfaces (APIs).

https://www.sktelecom.com/en/press/press_detail.do?page.page=1&idx=1492&page.type=all&page.keyword=



 

Sunday, November 29, 2020

U.S. to block China's SMIC from accessing U.S. investment

The Trump administration is planning to add Semiconductor Manufacturing International Corp (SMIC), China's leading chip producer, to a blacklist of alleged Chinese military companies, according to an exclusive report from Reuters. The move would restrict the company's access to U.S. investors. Reuters also reports that China Construction Technology Co Ltd, China International Engineering Consulting Corp, and China National Offshore Oil Corp (CNOOC) will also be added to the list.


Sunday, November 22, 2020

Marvell samples Alaska Octal Scalable mGig PHY

 Marvell has begun sampling its second-generation Alaska Octal Scalable mGig PHY family, its first optimized, low power dissipation, low footprint Octal 10M/100M/1G/2.5G/5G/10GBASE-T Ethernet transceivers with IEEE 1588v2 PTP support. 

The Octal mGig-10G 88X3580, a 10G PHY transceiver and the Octal mGig-5G  88E2580, a  2.5/5G PHY transceiver both exceed IEEE cable reach requirements, optimizing the number of access switch deployments and simplifying campus networking. The PHYs are the industry's first Octal 10G and 2.5/5G devices manufactured in 12nm FinFET advanced process technology, providing lower power consumption by up to 10% compared to the previous product generation.

Key features include:

  • Long cable reach performance: Exceeds IEEE standard requirements, 10-20% improvement compared with Marvell's previous generation Octal solution.
  • Low power consumption: The X3580 provides approximately 10% power reduction compared with Marvell's previous generation Octal solution.
  • Enhanced ESD/surge immunity
  • Enhanced EMI protection
  • Full Speed range (10M/100M/1G/2.5G/5G/10G)
  • Small footprint package (17mm x 17mm)
  • Dual media support (Optical and BASE-T)
  • USXGMII and legacy host interfaces (XFI, 5GBASE-R, 2500BASE-X, SGMII)

"Our new Octal mGig PHY family is designed to enable and accelerate emerging mobility and cloud applications by addressing the demand for bandwidth speed flexibility and lower power consumption," said Achyut Shah, vice president and general manager of the PHY BU at Marvell. "Together with our Prestera switches, the new high-density PHY devices offer an optimized performance and BOM cost solution. These make them ideal for mGig switch access use cases such as HD security cameras and Wi-Fi 6 access points including those for remote deployment beyond building structured wiring."

https://www.marvell.com/company/newsroom/marvell-expands-borderless-enterprise-portfolio-octal-scalable-mgig-phy-family.html

Thursday, October 29, 2020

Marvell to acquire Inphi for optical components business


Marvell Technology Group Ltd. agreed to acquire Inphi Corp. in a cash and stock transaction valued at approximately US$10 billion, consisting of $66 in cash and 2.323 shares of stock of the combined company for each Inphi share. Upon closing of the transaction, Marvell shareholders will own approximately 83% of the combined company and Inphi stockholders will own approximately 17% of the combined company.

Inphi’s high-speed electro-optics target data centers as well as wired and wireless carrier networks. The product portfolio includes Inphi transimpedance amplifiers (TIAs); drivers for 100G to 600G coherent optics; optical PHYs for signal recovery, retiming, grooming, error correction and gearbox operations; its COLORZ transceivers based on silicon photonics for 80/120km DWDM connectivity in a QSFP28 form factor; and its Canopus coherent Digital Signal Processors (DSPs)

Marvell said that by combining its storage, networking, processor, and security portfolio with Inphi’s  electro-optics interconnect platform, the combined company will deliver end-to-end technology leadership in data infrastructure. 

“Our acquisition of Inphi will fuel Marvell’s leadership in the cloud and extend our 5G position over the next decade,” said Matt Murphy, president and CEO of Marvell. “Inphi’s technologies are at the heart of cloud data center networks and they continue to extend their leadership with innovative new products, including 400G data center interconnect optical modules, which leverage their unique silicon photonics and DSP technologies. We believe that Inphi’s growing presence with cloud customers will also lead to additional opportunities for Marvell’s DPU and ASIC products.”

“Marvell and Inphi share a vision to enable the world’s data infrastructure and we have both transformed our respective businesses to benefit from the strong secular growth expected in the cloud data center and 5G wireless markets” said Ford Tamer, President and CEO of Inphi. “Combining with Marvell significantly increases our scale, accelerates our access to the next generations of process technology, and opens up new opportunities in 5G connectivity.”

Marvell also stated that intends to reorganize the combined company so that it will be domiciled in the United States, creating a U.S. semiconductor powerhouse with an enterprise value of approximately $40 billion. Upon closing, Ford Tamer, Inphi’s President and CEO, will join Marvell’s Board of Directors.

https://www.marvell.com/announcements/marvell-to-acquire-inphi.html

  • In 2016, Inphi acquired ClariPhy Communications, a provider of ultra-high-speed systems-on-chip (SoCs) for multi-terabit data, long haul and metro networking markets for $275 million in cash as well as the assumption of certain liabilities at the close. ClariPhy was one of the first merchant suppliers of coherent DSP technology. The company was based in Irvine, California.
  • In 2014, Inphi acquired Cortina Systems' High-Speed Interconnect and Optical Transport product lines for $52.5 million in cash and $73.5 million in stock.  In 2006, Cortina Systems acquired the assets of Intel's optical network components business for $115 million. Cortina was based in Sunnyvale, California.

Acacia and Inphi demo interoperability of 400ZR over 120 km

Acacia Communications and Inphi have demonstrated error-free links in 400ZR mode between Inphi’s COLORZ II QSFP-DD and Acacia’s 400ZR QSFP-DD module in Arista switches over a 120 km amplified link using 75GHz channel spacing. “Hyperscale network operators are planning to utilize interoperable 400ZR solutions to support growing bandwidth requirements between data centers,” said Josef Berger, AVP of Marketing, Optical Interconnect at Inphi. “This...

Inphi acquires assets in Vietnam from Arrive Technologies

Inphi has acquired certain assets from Arrive Technologies, located in Ho Chi Minh City, Vietnam. Financial terms were not disclosed.

Arrive Technologies, founded in 2001, has 112 employees with strong design capabilities in embedded software, digital ASIC, post-silicon validation, and FPGA emulation. The team has designed highly complex transport framers and products including pseudowire and circuit emulation functions with domain expertise including, but not limited to, OTN/SONET, FEC, PTP, and Security (IPsec). Arrive had been engaged with many of Inphi’s system OEM customers in the cloud, telecom, and 5G markets. 

Inphi said the addition of these resources will provide Inphi with front-end design, verification, validation and firmware skills that complement Inphi’s existing design teams in Singapore and Vietnam.

Inphi samples 800G 7nm PAM4 DSP

Inphi is sampling its new Spica 800G 7nm PAM4 DSP, the world’s first 800Gbps or 8x100Gbps PAM4 DSP to enable 800G optical transceiver modules in QSFP-DD800 or OSFP form factors.

Inphi's highly integrated Spica 800G platform includes the company's high-performance, low power PAM4 DSPs alongside its companion market-leading low power linear driver and TIAs.

The company said its Spica 800Gbps PAM4 DSP with integrated 56GBaud driver, enables either 2x400Gbps or 8x100Gbps optical modules with 100Gbps per lane electrical interfaces. Applications could include 800Gbps / 8x100Gbps optical interconnects in a compact form factor for single-mode fibers or multimode fibers. The Spica platform could be matched with Inphi’s 112Gbps Capella SerDes IP for next-generation AI processors and switches.

Inphi samples its 3rd gen, single-lambda PAM4

Inphi has begun sampling its Porrima Gen3 Single-Lambda PAM4 platform based on 7nm technology and optimized for hyperscale data center networks. The new design offers an expanded feature set and enhanced direct drive capability, further expanding the breadth of lasers that can be used with the integrated laser driver. The new platform is also designed to reduce total module power consumption to less than 8W for 400Gbps DR4/FR4 mode in the QSFP-DD form factor.

“Porrima Gen3 is another prime example of our ongoing dedication to this market, by increasing investments to exceed customer needs and stay ahead of the competition,” said Eric Hayes, SVP, Networking Interconnect, Inphi. “Not only are we delivering better performance and lower power with this third-generation PAM4 solution, but we are also making it easy for customers to make a smooth transition. This will accelerate adoption of this total solution and maintain our market leadership position.”

Inphi intros its 2nd gen 112Gbps SerDes in 7nm

Inphi released its second-generation, high performance 112Gbps SerDes IP solution in 7nm. Inphi said its new Capella SerDes IP is designed to ensure high performance across the most demanding environments for network connectivity and data transmission. The announcement builds on Inphi’s track record of having shipped over a million 56Gbps and 112Gbps ports to date. “Delivering the next generation of SerDes IP technology is a significant milestone...

NeoPhotonics began sampling its new 400ZR ClearLight OSFP transceiver to a leading cloud -related customer. The new transceiver utilizes NeoPhotonics Silicon Photonics Coherent Optical Subassembly (COSA) and low power consumption, ultra-narrow linewidth Nano-ITLA tunable laser, combined with the latest generation of 7 nm DSP, to provide full 400ZR transmission in a standard data center OSFP form factor. NeoPhotonics said its new 400ZR ClearLight...

Inphi milestone: 100,000 COLORZ silicon photonics PAM4 units shipped

Inphi noted a company milestone -- the shipment of more than 100,000 COLORZ units, its Silicon Photonics PAM4 platform solution for 80km DWDM connectivity in a QSFP28 form factor. Inphi said its unique approach in integrating PAM4 CMOS with silicon photonics enables the platform to achieve a 60% in cost and a 75% in power savings. Accomplishing the COLORZ ramp to 100k within a span of only three years also validates the network inflection point...


Inphi to acquire eSilicon for $226 million

Inphi Corporation agreed to acquire eSilicon for $216 million in both cash and the assumption of debt.

“The Inphi team is excited to enhance our value proposition to our cloud and telecom customers with the addition of the eSilicon team and IP,” said Ford Tamer, president and CEO of Inphi. “eSilicon adds to Inphi world-class 2.5D packaging, SerDes, custom silicon and operations teams. Just as we successfully leveraged our Cortina and Clariphy acquisitions, eSilicon will advance our shared commitments in driving successful customer engagement, industry-leading innovation, and best of class execution.”

Inphi lists the following drivers for the acquisition:

  • Combine Inphi’s DSP, TiA, Driver and SiPho disciplines with eSilicon’s 2.5D packaging and custom silicon design capabilities and accelerate the roadmap for electro-optics, 5nm advanced CMOS process node, and custom DSP solutions
  • Augment Inphi’s existing SerDes team and resources
  • Extend Inphi’s addressable market in Cloud data center networking and Telecom 5G infrastructure with top tier OEM customers
  • Expand Inphi’s presence into new, strategic geographies for talent acquisition with engineering design centers in Italy, Romania, Vietnam, and Spain and operations in Malaysia
  • Add between $80 to $120 million to 2020 revenue, be accretive to 2020 EPS and both the 2021 revenue and EPS growth rates
  • Increase Inphi’s operational scale with suppliers, lowering costs and resulting in financial leverage
  • Result in Inphi paying about 2.2X 2020 revenue in a combination of cash and debt assumption

Untether AI leverages at-memory computation for inference processing

Untether AI, a start-up based in Toronto, introduced its "tsunAImi" accelerator cards are powered by four of its own runAI200 processors, which feature a unique at-memory compute architecture that aims to re-think how computation for machine learning is accomplished. The company says that 90 percent of the energy for AI workloads in current processing architectures is consumed by data movement, transferring the weights and activations between external memory, on-chip caches, and finally to the computing element itself. 

Untether AI says it is able to deliver two PetaOperations per second (POPs) in its new standard PCI-Express cards -- more than two times any currently announced PCIe cards, which translates into over 80,000 frames per second of ResNet-50 v 1.5 throughput at batch=1, three times the throughput of its nearest competitor. For natural language processing, tsunAImi accelerator cards are rated at more than 12,000 queries per second (qps) of BERT-base, four times faster than any announced product.

“For AI inference in cloud and datacenters, compute density is king. Untether AI is ushering in the PetaOps era to accelerate AI inference workloads at scale with unprecedented efficiency,” said Arun Iyengar, CEO of Untether AI.

“When we founded Untether AI, our laser focus was unlocking the potential of scalable AI, by delivering more efficient neural network compute,” said Martin Snelgrove, co-founder and CTO of Untether AI. “We are gratified to see our technology come to fruition.”

The imAIgine SDK is currently in Early Access (EA) with select customers and partners. The tsunAImi accelerator card is sampling now and will be commercially available in 1Q2021.

Untether AI is funded by Radical Ventures and Intel Capital. 

http://www.untether.ai

Wednesday, October 7, 2020

Marvell intros automotive Gigabit Ethernet PHY with MACsec

 Marvell introduced an automotive gigabit Ethernet PHY solution with integrated media access control security (MACsec).

Marvell said MACsec will fortify in-vehicle networking by securing data exchange on a hop-by-hop basis and prevents Layer 2 security threats such as intrusion, man-in-the-middle, and replay attacks. Marvell's new Open Alliance TC10 compliant, dual speed 100/1000 BASE-T1 88Q222xM Ethernet PHY enables energy efficient, secure in-vehicle networks and assists in achieving functional safety compliance at the system level.

Automotive networks rely heavily on partial networking in which some segments are hibernated and woken up on demand. Marvell's new gigabit PHY supports the Open Alliance TC10 for sleep mode and wake-up, tailored for automotive use cases. 

"Marvell is committed to developing innovative solutions for the automotive market and offers the industry's largest portfolio of secure Ethernet switches and PHYs," said Amir Bar-Niv, vice president of Marketing of the Automotive Business Unit at Marvell. "We are extremely proud to introduce the industry's first automotive gigabit Ethernet PHY that integrates Layer 2 security through MACsec while also delivering best-in-class lower power performance that meets the most stringent power budget. Marvell's 88Q222x solution is based on the Automotive QMS Process and comes with functional safety collateral assisting tier-1s and OEMs in fulfilling ISO 26262 at a system level."

https://www.marvell.com/products/automotive/88q222xm.html


Monday, October 5, 2020

NVIDIA unveils DPUs and Data-Center-Infrastructure-on-a-Chip SDK

 NVIDIA has begun sampling its second-generation family of BlueField data processing unit (DPUs) for accelerating data center infrastructure.

The new BlueField-2 DPU is designed to offload critical networking, storage and security tasks from server CPUs. The company says a single chip can deliver the same data center services that could consume up to 125 CPU cores. This frees up valuable CPU cores to run a wide range of other enterprise applications.

NVIDIA’s current DPU lineup includes two PCIe products:

  • The NVIDIA BlueField-2 DPU, which features all of the capabilities of the NVIDIA Mellanox ConnectX-6 Dx SmartNIC combined with Arm cores. Fully programmable, it delivers data transfer rates of 200 Gbps and accelerates key data center security, networking and storage tasks, including isolation, root trust, key management, RDMA/RoCE, GPUDirect, elastic block storage, data compression and more.
  • The NVIDIA BlueField-2X DPU, which includes all the key features of a BlueField-2 DPU enhanced with an NVIDIA Ampere GPU’s AI capabilities that can be applied to data center security, networking and storage tasks. Drawing from NVIDIA’s third-generation Tensor Cores, it is able to use AI for real-time security analytics, including identifying abnormal traffic, which could indicate theft of confidential data, encrypted traffic analytics at line rate, host introspection to identify malicious activity, and dynamic security orchestration and automated response.

BlueField-2 DPUs are sampling now and expected to be featured in new systems from leading server manufacturers in 2021. BlueField-2X DPUs are under development and are also expected to become available in 2021.

NVIDIA says its BlueField DPUs are being adopted by leading server manufacturers worldwide, including ASUS, Atos, Dell Technologies, Fujitsu, GIGABYTE, H3C, Inspur, Lenovo, Quanta/QCT and Supermicro.

NVIDIA is developing a novel data-center-infrastructure-on-a-chip (DOCA) architecture and programming that is intended to be analogous to its CUDA environment for GPUs. A new NVIDIA DOCA software development kit enables developers to rapidly create applications and services on top of NVIDIA BlueField DPUs. he DOCA SDK provides industry-standard open APIs and frameworks, including Data Plane Development Kit (DPDK) and P4 for networking and security and the Storage Performance Development Kit (SPDK) for storage. 

  • NVIDIA is also participating in VMware's recently announced Project Monterey to integrate SmartNICs with VMware Cloud Foundation.
  • Red Hat plans to offer support for BlueField-2 DPUs with Red Hat Enterprise Linux and Red Hat OpenShift, components of Red Hat’s open hybrid cloud portfolio, which is used by 95 percent of the Fortune 500.
  • Canonical announced support of BlueField-2 DPUs and DOCA in its Ubuntu Linux platform, the most popular operating system among public clouds.
  • Check Point Software Technologies, a leading cybersecurity provider, is integrating BlueField-2 DPUs into its technologies, which more than 100,000 organizations worldwide use to protect themselves from cyberattacks.




http://www.nvidia.com


Sunday, October 4, 2020

U.S. DoD backs Intel for semiconductor packaging tech

The U.S. Department of Defense awarded a contract to Intel to enable the U.S. government to access Intel’s state-of-the-art semiconductor packaging capabilities in Arizona and Oregon.

The project, which is supported by the DoD's State-of-the-Art Heterogeneous Integration Prototype (SHIP) program,  is executed by the Naval Surface Warfare Center, Crane Division, and administered by the National Security Technology Accelerator.

The second phase of SHIP will develop prototypes of multichip packages and accelerate advancement of interface standards, protocols and security for heterogeneous systems. SHIP prototypes will integrate special-purpose government chips with Intel’s advanced, commercially available silicon products, including field programmable gate arrays, application-specific integrated circuits and CPUs. This combination of technologies provides new paths for the U.S. government’s industry partners to develop and modernize the government’s mission-critical systems while taking advantage of Intel’s U.S. manufacturing capabilities.

Heterogeneous packaging allows the assembly of multiple, separately manufactured integrated circuit dies (chips) onto a single package to increase performance while reducing power, size and weight. SHIP provides the U.S. government access to Intel’s advanced heterogeneous packaging technologies, including embedded multi-die interconnect bridge (EMIB), 3D Foveros and Co-EMIB (combining both EMIB and Foveros).

“Intel and the U.S. government share a priority to advance domestic semiconductor manufacturing technology. The SHIP program will enable the Department of Defense to take advantage of Intel’s advanced semiconductor packaging capabilities, diversifying their supply chain and protecting their intellectual property while also supporting ongoing semiconductor R&D in the U.S. and preserving critical capabilities onshore,” stated Jim Brinker, president and general manager of Intel Federal LLC.

“To ensure that the U.S. defense industry base can continue to deliver state-of-the-art electronics for national security, it is imperative that the Department of Defense (DoD) partners with leading U.S. semiconductor companies," Nicole Petta, principal director of microelectronics, Office of the Under Secretary of Defense for Research and Engineering. "The DoD microelectronics roadmap recognizes the importance of strategic partnerships with industry. The roadmap also prioritizes and recognizes that as process scaling slows, heterogeneous assembly technology is a critical investment for both the DoD and our nation. SHIP directly contributes to advancing the objectives outlined in the DoD roadmap and the DoD looks forward to working with Intel, a world leader in this technology.”

http://www.intel.com




In 2018, Intel demonstrated a new 3D packaging technology, called "Foveros," which for the first time brings 3D stacking to logic-on-logic integration. Foveros will will allow products to be broken up into smaller “chiplets,” where I/O, SRAM and power delivery circuits can be fabricated in a base die and high-performance logic chiplets are stacked on top. The first Foveros product will combine a high-performance 10nm compute-stacked chiplet with a low-power 22FFL base die. 

Tuesday, September 22, 2020

Arm expands its Neoverse data center server CPU porfolio

Arm is unveiling two new platforms in its Neoverse silicon portfolio for data centers CPUs: 

  • the Arm Neoverse V1 platform, delivering a single-threaded performance uplift of more than 50% over N1 and aimed at applications more reliant on CPU performance and bandwidth. Neoverse V1 supports Scalable Vector Extensions (SVE), which enables execution of single-instruction multiple dispatch (SIMD) integer, bfloat16, or floating-point instructions on wider vector units using a software programming model that’s agnostic to the width of the unit. Arm says SVE will ensure portability and longevity of the software code, along with efficient execution. Potential markets include high-performance cloud, HPC, and machine learning.
  • the Neoverse N2, which is the second-generation N-series platform, and aimed at the scale-out performance needs of applications across a range of use cases, from cloud to SmartNICs and enterprise networking, to power-constrained edge devices.  Neoverse N2 offers 40% higher single-threaded performance, compared to Neoverse N1, and retains the same level of power and area efficiency as Neoverse N1.
Arm's Neoverse roadmap now extends from 7nm devices currently in production, to 5nm designs in 2021 and 3nm in 2022.


Arm cited growing momentum for its Neoverse silicon across a range of data center applications. Operating systems and hypervisors, Xen, KVM, Docker containers, and, increasingly, Kubernetes have all announced support for Arm. 

http://www.arm.com



Thursday, August 20, 2020

DARPA’s Electronics Resurgence Initiative signs Arm

Arm today announced a three-year partnership agreement with the U.S. Defense Advanced Research Projects Agency (DARPA), establishing an access framework to all commercially available Arm technology.

Under DARPA’s Electronics Resurgence Initiative, the research community that supports DARPA’s programs will gain access to Arm’s IP, tools and support programs.

“The span of DARPA research activity opens up a huge range of opportunities for future technological innovation,” said Rene Haas, president, IP Products Group, Arm. “Our expanded DARPA partnership will provide them with access to the broadest range of Arm technology to develop compute solutions supported by the world’s largest ecosystem of tools, services and software.”

“DARPA’s programs within the Microsystems Technology Office (MTO) focus on the most advanced challenges in microelectronics; equipping our community with best in class technologies is essential not only for break-through scientific and engineering advances, but also for improved transition into military and commercial applications,” stated Serge Leef, who leads design automation and secure hardware programs in MTO.

https://www.darpa.mil/work-with-us/electronics-resurgence-initiative

Tuesday, August 18, 2020

Fungible announces its DPU for scale-out data centers

Fungible, a start-up based in San Jose, California, unveiled its Fungible Data Processing Unit (Fungible DPU), a microprocessor optimized for data interchange and data-centric computation in scale-out architectures.

Fungible describes its DPU as the "third socket" in data centers, complementing the CPU and GPU, and delivering significant gains in performance, footprint and cost efficiencies for next-generation, scale-out networking, storage, security, and analytics platforms.  The company cites two core innovations that are tightly interwoven:

  • A programmable data-path engine that executes data-centric computations at extremely high speeds, while providing flexibility comparable to general-purpose CPUs. The engine is programmed in C using industry-standard toolchains and is designed to execute many data-path computations concurrently. 
  • A new network engine that implements the endpoint of a high-performance TrueFabric that provides deterministic low latency, full cross-section bandwidth, congestion and error control, and high security at any scale (from 100s to 100,000s of nodes). The TrueFabric protocol is fully standards-compliant and interoperable with TCP/IP over Ethernet, ensuring that the data center leaf-spine network can be built with standard Ethernet switches and standard electro-optics and fiber infrastructure.

Fungible is launching two versions of its DPU:
  • Fungible F1 DPU – an 800Gbps processor designed specifically for high performance storage, analytics and security platforms.
  • Fungible S1 DPU – a 200Gbps processor optimized for host-side use cases including bare metal virtualization, storage initiator, NFVi/VNF applications and distributed node security.
Fungible also provides a full suite of software that enables the Fungible DPU and the products it powers to be used "out of the box". This includes data-path stacks, host drivers and agents for x86, and a set of centralized cluster services that provides management, control and visibility of a large number of Fungible DPU-enabled products.

"The Fungible DPU is purpose built to address two of the biggest challenges in scale-out data centers – inefficient data interchange between nodes and inefficient execution of data-centric computations," said Pradeep Sindhu, CEO and Co-Founder of Fungible. "Data-centric computations are increasingly prevalent in data centers, with important examples being the computations performed in the network, storage, security and virtualization data-paths. Today, these computations are performed inefficiently by existing processor architectures. These inefficiencies cause overprovisioning and underutilization of resources, resulting in data centers that are significantly more expensive to build and operate. Eliminating these inefficiencies will also accelerate the proliferation of modern applications, such as AI and analytics."

https://www.fungible.com/


Fungible raises $200 million for Data Processing Units (DPUs)

Fungible, a start-up based in Santa Clara, California, closed $200 million in Series C financing for its efforts to create an entirely new category of programmable processor.

The Fungible Data Processing Unit (DPU) aims to deliver an order of magnitude improvement in the execution of data-centric workloads. The company sees its DPU as a fundamental building block for next-generation data centers.

Fungible has not yet announced its first products. In previous blog posts, Fungible has talked about Composable Disaggregated Infrastructure (DCI), where compute and storage resources are stored in separate servers and interconnected by a very high bandwidth, reliable and low-latency IP over Ethernet (IPoE) network fabric.

Fungible was founded by Pradeep Sindhu and Bertrand Serlet. Sindhu previously founded Juniper Networks, held roles as CEO and CTO, and is now chief scientist. Serlet previously founded a storage startup and before that was senior vice president of software engineering at Apple.

The latest funding was led by the SoftBank Vision Fund with participation from Norwest Venture Partners and existing investors, including Battery Ventures, Mayfield Fund, Redline Capital and Walden Riverwood Ventures. Fungible has raised $300 million to date.

SiFive and Innovium enter collaboration

SiFive and Innovium, announced a collaboration to drive faster innovation in switch silicon solutions.

SiFive specializes in RISC-V processor IP and silicon solutions. Innovium is known for its networking switch silicon for cloud and edge data centers.

The companies are collaborating on new designs that incorporate SiFive E2-Series processor cores to extend Innovium’s programmable switch silicon.

Innovium’s TERALYNX offers customers a highly differentiated and comprehensive programmable switch silicon portfolio, from 1 to 25.6Tbps performance and an architecture scaling to 51.2Tbps+, with consistent features and software.

“As Innovium’s highly successful TERALYNX switches ramp in Cloud and Edge data centers, we continue to invest in an industry-leading roadmap for next-generation networks,” said Rajiv Khemani, CEO of Innovium, Inc. “We are pleased to use SiFive’s processor IP in our products for additional flexible and programmable capabilities in the areas of management and configuration.”

“SiFive’s winning processor portfolio is well suited to new designs for datacenter infrastructure thanks to the highly-efficient, silicon-proven, configurable cores we offer,” said Dr. Naveed Sherwani, Chairman, President & CEO of SiFive. “The data center market is searching for efficient and scalable networking solutions that, through collaborating with Innovium, we can help provide.”

SiFive raises $61 million for RISC-V

SiFive, a start-up specializing in RISC-V processor IP and silicon solutions,  raised $61 million in a Series E round.

SiFive, which is based in San Mateo, California, develops a range of processor cores, accelerators, and SoC IP to create domain-specific architecture that will enable efficient, high-performance computing solutions. Recently, SiFive announced the SiFive 20G1 update for SiFive Core IP, enabling significant enhancements for performance, power, area, and features, with pre-integrated SiFive Shield, for whole SoC security, and SiFive Insight advanced trace and debug capabilities.

The latest funding round was led by SK hynix, joined by new investor Prosperity7 Ventures, with additional funding from existing investors, Sutter Hill Ventures, Western Digital Capital, Qualcomm Ventures LLC, Intel Capital, Osage University Partners, and Spark Capital.

Innovium raises $170 million for its switching silicon

Innovium, a start-up based in San Jose, California, raised $170 million for its switching silicon solutions cloud and edge data centers.

The new funding round included investments from Premji Invest, DFJ Growth, funds and accounts managed by BlackRock, and multiple strategic investors, along with existing investors including Greylock, Capricorn, WRVI, Qualcomm Ventures, Redline, S-Cubed Capital and DAG

. Innovium said this latest funding makes it the first network silicon company to achieve billion-dollar valuation "unicorn" status.

Earlier this year, Innovium unveiled its TERALYNX 8 silicon boasting 25.6Tbps switch with 112G SerDes

In addition, Innovium noted the following milestones during 1H 2020:

  • Continued volume production ramp of TERALYNX 7
  • Ramping TERALYNX 5 shipments for ToR, Edge & 5G customer designs
  • Revenue growth of over 5x in 1H 2020 vs 1H 2019
  • Achieved over 20% market share in 50G WW SerDes shipments and emerged as the only credible silicon diversity option [1]
  • Wins, deployments and trials at majority of top 25 Cloud customers in the world

“We are delighted at the strong adoption at leading OEM, Cloud and ODM customers for our TERALYNX® family, which resulted in over 20% market share for 50G SerDes switch silicon in our first year of shipments. This additional funding, achieved despite ongoing macroeconomic uncertainty, validates our vision, execution and momentum in a multi-billion secular high-growth market,” said Rajiv Khemani, Co-founder and CEO of Innovium.

“Data centers are expected to see secular long-term expansion from Cloud, 5G, AI and remote-work applications. Innovative TERALYNX switch silicon products from Innovium have already been adopted by world’s leading hyperscale Cloud providers and leading OEMs including Cisco. We are excited to partner with Innovium for its roadmap innovation and help accelerate go-to-market ramp up,” said TK Kurien, Managing Partner and Chief Investment Officer at Premji Invest.

https://www.innovium.com/

Innovium pushes switching silicon to 25.6 Tbps with support for 112G PAM4

Innovium unveiled its TERALYNX 8 networking switch silicon featuring a massive 25.6 Tbps capacity and support for 112G PAM4 SerDes I/O. This next-generation TERALYNX 8 design features deep programmability, the largest on-chip buffers, and advanced telemetry capabilities.

Innovium's TERALYNX 8 switch, which is aimed at hyperscale data centers and which is expected to sample in the second half of 2020, could be used for highly compact, highest port-density single-chip switches for 100G to 800G configurations, including 1RU, 32 x 800G switch. The silicon will be delivered in a single 7nm die fabricated by TSMC.

Innovium confirmed that its current generation, 12.7 Tbps switching silicon is already being used by numerous commercial customers, including some of the biggest cloud provider networks.