Showing posts with label Silicon. Show all posts
Showing posts with label Silicon. Show all posts

Monday, December 9, 2019

Andes' RISC-V processor qualified for Amazon FreeRTOS

Andes Technology's Corvette-F1 N25 platform is one of the first RISC-V platforms qualified for Amazon FreeRTOS.

Amazon FreeRTOS is an open source operating system for microcontrollers from Amazon Web Services (AWS) designed for small, low-power edge devices.

“IoT, and AIoT, will be a big addressable market for RISC-V CPU,” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “By leveraging the advantages of Amazon FreeRTOS and Andes RISC-V platform, we can provide developers using Amazon FreeRTOS additional development platform choices and strengthen the Andes RISC-V IoT solutions for our customers.”

Andes' Corvette-F1 N25 platform is a FPGA-based Arduino-compatible evaluation platform. It comes with a 32-bit RISC-V AndesCore N25 running at 60MHz, 4MB Flash, 256KB instruction SRAM and 128KB data SRAM, and AndeShape AE250 Platform IP with rich peripherals such as GPIO, I2C, PWM, SPI, and UART. It also contains an on-board wireless module supporting IEEE 802.11 b/g/n.

http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-n25/

Cambium adopts Sequans’ LTE-Advanced chipset for CPE

Cambium Networks has adopted Sequans’ LTE-Advanced chipset platform, Cassiopeia, for two Customer Premises Equipment (CPE) designs for global markets. Both are high-performance integrated access devices with which Cambium Networks aims to meet the integrated data, voice, and internet access needs of its residential, business, and enterprise customers.

  • cnRanger 2 GHz Tyndall 101. An LTE Category 4 Subscriber Module with 14 dBi integrated panel antenna supporting TD-LTE Bands 38, 40 and 41. Available now.
  • cnRanger 3 GHz Tyndall 201. An LTE Category 6 Subscriber Module with 19 dBi integrated dish antenna supporting TD-LTE Bands 42, 43 and 48. Available mid-2020.

The LTE-Advanced chip inside the new Cambium Networks CPE devices is Sequans’ Cassiopeia LTE-Advanced chip platform, a member of Sequans’ StreamrichLTE family of products for broadband high-performance devices. Cassiopeia is compliant with 3GPP Release 10 specifications and supports highly flexible dual-carrier aggregation that allows the combination of any two carriers of any size up to 20 MHz each, contiguous or non-contiguous, inter-band or intra-band. Cassiopeia also supports other Release 10 enhancements such as new MIMO schemes, enhanced inter-cell interference coordination (eICIC) schemes for heterogeneous networks (HetNets), and improvements to eMBMS (evolved multimedia broadcast multicast service) or LTE broadcast. Cassiopeia features Sequans’ advanced receiver technology for improved performance.

Wednesday, December 4, 2019

Qualcomm packs a punch with its Snapdragon 865 5G

Qualcomm unveiled its latest flagship mobile chipset- the Snapdragon 865 5G Mobile Platform, which combines an advanced 5G Modem-RF System with the processing capabilities to power the next generation of flagship mobile devices.

At a media event in Hawaii, Qualcomm execs previewed camera, audio, and gaming experiences that made possible by the whopping 15 TOPS of AI performance delivered by the new 7nm chipset. This includes the option for real-time translations of a phone conversation to another language. Imaging possibilities include the ability to capture in 4K HDR with over a billion shades of color, capture 8K video, or snap massive 200-megapixel photos.

Snapdragon 865 5G highlights:

  • Compatible with both 5G standalone and non-standalone modes  
  • Multi-gigabit downlink speeds of up to 7.5 Gbps 
  • Support for all key regions and frequency bands from 5G mmWave and sub-6, TDD and FDD, to SA and NSA modes
  • Dynamic Spectrum Sharing (DSS)
  • 5G mmWave specs: 800 MHz bandwidth, 8 carriers, 2x2 MIMO
  • 5G sub-6 GHz specs: 200 MHz bandwidth, 4x4 MIMO
  • LTE including CBRS support
  • 5th generation Qualcomm AI Engine packs 2x the performance of its predecessor. Qualcomm Hexagon Tensor Accelerator pushes 15 trillion operations per second
  • Dolby Vision video capture
  • 8K video recording
  • 200 megapixel photos
  • Simultaneously captures 4K HDR video and 64 MP photos
  • Qualcomm Sensing Hub ensures highly accurate voice detection and always-on contextual awareness for smarter virtual assistants
  • Qualcomm Adreno 650 GPU delivers up to 25% performance boost from its predecessor
  • Wi-Fi Standards: 802.11ax (Wi-Fi 6), 802.11ax (Wi-Fi 6-ready), 802.11ad, 802.11ay, 802.11ac Wave 2, 802.11a/b/g, 802.11n
  • Qualcomm Wi-Fi 6 technology features: MU-MIMO (Uplink and Downlink), 8x8 sounding, OFDMA (Uplink and Downlink), 1024 QAM, Dual-band simultaneous (DBS), WPA3 security support, Target Wake Time
  • Bluetooth 5.1
  • USB 3.1, USB-C


“Snapdragon 865 supports the world’s most advanced 5G connectivity and features, raising the bar for what a mobile device should be,” said Alex Katouzian, senior vice president and general manager, mobile, Qualcomm Technologies, Inc. “It’s the culmination of Qualcomm’s more than 30 years of wireless leadership and innovation.”

https://www.qualcomm.com/products/snapdragon-865-5g-mobile-platform

Tuesday, December 3, 2019

AWS previews EC2 instances running its own Graviton2 processors

AWS offered a sneak peek at its next generation of Arm-based EC2 instances powered by its own Graviton2 processor.

Graviton2 is a custom AWS design that is built using a 7nm manufacturing process and based on 64-bit Arm Neoverse cores. AWS says it can deliver up to 7x the performance of the A1 instances, including twice the floating point performance. Additional memory channels and double-sized per-core caches speed memory access by up to 5x.

AWS estimates up to 40% better price performance over comparable current generation instances for a wide variety of workloads, including application servers, micro-services, high-performance computing, electronic design automation, gaming, open-source databases, and in-memory caches.

Graviton2 will be able to run Amazon Linux 2, Red Hat Enterprise Linux, Ubuntu, SUSE Linux Enterprise Server, Fedora, FreeBSD, and Debian. Container support includes Docker, Amazon Elastic Kubernetes Service, Amazon Elastic Container Service, and Firecracker.

https://aws.amazon.com/ec2/graviton/

Sunday, December 1, 2019

Panasonic sells its semiconductor group to Taiwan's Nuvoton

Panasonic Corporation will transfer its semiconductor business to Taiwan-based Nuvoton Technology, a division of Winbond, in an all-cash transaction. Financial terms were not disclosed.

Panasonic Semiconductor Solutions, located in Nagaokakyo City, Kyoto, is a leading global supplier of semiconductor devices and solutions with products that focus on “Sensing” technologies such as Image Sensors, Image / Digital Signal Processors, “Microcontroller” technologies such as MCU, IC Card, Battery Management, Power Management and ”Component” technologies such as MOSFET, RF-GaN and Laser Diode.

Panasonic said it decided to exit semiconductors due to the aggressive expansion of competitors that would require huge investments to keep up.

Thursday, October 24, 2019

Intel intros Tremont microarchitecture

Intel unveiled Tremont, its next-generation, low-power x86 microarchitecture promising significant IPC (instructions per cycle) gains gen-over-gen compared with Intel’s prior low-power x86 architectures.

Tremont is aimed at compact, low-power packages and innovative form factors for client devices, creative applications for the internet of things (IoT), data center products, etc.

Tremont is integrated within a wider set of silicon IPs in Lakefield, which will power innovative devices like the recently announced dual-screen Microsoft Surface Neo. Iy includes several advancements in ISA (instruction set architecture), microarchitecture, security and power management. Specifically, Tremont’s unique 6-wide (2x3-wide clustered) out-of-order decoder in the front end allows for a more efficient feed to the wider back end, which is fundamental for performance.

The announcement was made at this week's Linley Fall Processor Conference 2019 in Silicon Valley.

https://newsroom.intel.com/wp-content/uploads/sites/11/2019/10/introducing-intel-tremont-microarchiture.pdf

Monday, October 14, 2019

Metanoia updates its Gfast chipset

Metanoia Communications, a subsidiary of Elan Microelectonics based in Taiwan and developer of high-speed xDSL and Gfast PHY chipsets for wireline broadband applications, introduced its latest family of chipsets that supports all the ITU-T Gfast (212MHz profile) and VDSL2 (35MHz profile) standards and builds on Metanoia’s existing Gfast, VDSL2 and ADSL2/2+ technology. With its MT-x2331 product family, Metanoia will deliver the industry first next generation broadband access xDSL PHY chipset for multiple applications including home gateways, low density xDSL Central Office systems and standalone xDSL termination, such as SFP modules.

Metanoia MT-x2331 series is a chipset family that supports all existing ITU-T Gfast, VDSL2 and ADSL2/2+ standards. Each member of the family, namely, the MT-V2331 (VDSL2 only), the MT-G2331 (Gfast only) and the MT-C2331 (for both G.fast and VDSL2), comprises a DMT (Discrete Multi-Tone) chip and an AFE (Analog Front End) chip, each in a single small package, thereby greatly minimizing the board size to meet the requirements and form factors of a wide variety of different applications.

“Bringing this new programmable architecture to life enables us to deliver a unique low power and highly integrated xDSL PHY solution with future-proof capabilities for the Operators to upgrade their WAN solutions in the field as standards and requirements develop,” added Didier Boivin, executive vice president at Metanoia Communications. “Our combined product offering with NXP will enable customers to address all xDSL market segments, starting from a simple single-port PHY to a sophisticated high-end home gateway with WiFi capabilities, using the same core xDSL technology.”

http://www.metanoia-comm.com/

Tuesday, October 8, 2019

Nokia aims Quillion chipset at next gen access

Nokia outlined plans for a new family of chipsets to power next-generation massive scale access networks.

The forthcoming "Quillion" chipset will allow operators to introduce 10G PON in their fiber networks and to serve more users from G.fast access nodes. For next-generation fiber access networks, the Quillion chipset powers Nokia’s 16-port Multi-PON line card, which supports both GPON and NG-PON on each port. This allows operators with an existing GPON network to simply “switch on” NG-PON services on each port without recabling or disrupting the GPON service.

Nokia said Quillion is also optimized to allow for low-latency applications that are critical for 5G transport and has built-in programmability to support intents that pave the way toward automated workflows, such as network slicing for 5G transport.

In addition, the Quillion chipset supports copper infrastructure access, including the highest density G.fast and Vplus solutions on the market.

Sandra Motley, President of Fixed Networks at Nokia, said: “In a 5G world, consumers will expect a gigabit experience regardless if they are at home or on the go. Our Quillion chipset is designed to deliver gigabit broadband to every home, using  broadband technologies like fiber to complement 5G in massive scale access networks. This allows operators to efficiently connect more people with higher speeds, and positively impacts their business case.”

Arm to support custom instructions for Cortex CPUs

Arm will introduce a new custom instructions feature for its Armv8-M architecture. The approach gives chip designers the ability to add unique application-specific features into Cortex-M33 CPUs.

Arm Custom Instructions will initially be implemented in Arm Cortex-M33 CPUs starting in the first half of 2020 at no additional cost to new and existing licensees, enabling SoC designers to add their own instructions for specific embedded and IoT applications without risk of software fragmentation.

“A world of a trillion secure intelligent devices will be built on a diversity of complex use cases requiring increased synergy between hardware and software design,” said Dipti Vachani, senior vice president and general manager, Automotive and IoT Line of Business, Arm. “We have engineered Arm Custom Instructions to fuel closer hardware and software co-design efforts toward achieving application-specific acceleration while unlocking greater device differentiation.”

https://www.arm.com/company/news/2019/10/arm-enables-custom-instructions-for-embedded-cpus

Tuesday, September 3, 2019

Semtech debuts XGSPON chipset

Semtech announced production availability of itsGN7153B combo chip and GN7055B multi-rate burst mode transimpedance amplifier (TIA) for XGSPON Optical Line Terminals (OLTs).

Semtech's GN7153B is a combo chip supporting OLT transmit and receive signals in a fully integrated solution.

On the receive side, the GN7153B supports both XGPON (2.5G) and XGSPON (2.5G/10G) signals, while the transmit data path features Semtech’s 10G EML driver with ClearEdge CDR technology to effectively reset the signal jitter budget. Transmit path optimization can be accomplished through an I2C programmable PLL loop bandwidth control and a variety of jitter filter modes. The EML driver includes eye-shaping features and an Automatic Power Control (APC) loop to deliver best-in-class transmit eye quality. The burst mode receive data path includes a multi-rate 2.5G/10G limiting amplifier with a fast burst mode signal detect function, integrated discharge circuit and reset for short settling time.

Semtech said its high sensitivity burst mode TIA (GN7055B) is designed for XGSPON OLT applications. Using an external reset signal, the burst mode TIA meets the convergence time and burst dynamic range requirements of XGSPON 2.5G and 10G.The device features a fast Automatic Gain Control (AGC) loop to enable high dynamic range in burst mode applications. The GN7055B is offered in die form, supports industrial temperature range and uses a single 3.3V power supply.

“XGSPON will bring a new generation of faster optical broadband services for home and business to the largest sector of the PON market,” said Dr. Timothy Vang, Vice President of Marketing and Applications for Semtech’s Signal Integrity Products Group. “Our chipset contributes to that growth by bringing high performance and low cost.”

http://www.semtech.com/optical

Wednesday, August 21, 2019

Xilinx's Virtex UltraScale+ FPGA boasts 35 billion transistors

Xilinx has expanded its 16nm Virtex UltraScale+ family to now include the world's largest FPGA — the Virtex UltraScale+ VU19P.

The new VU19P FPGA boasts 35 billion transistors, the highest logic density and I/O count on a single device, according to Xilinx. The device could be used for enabling emulation and prototyping of tomorrow's most advanced ASIC and SoC technologies, as well as test, measurement, compute, networking, aerospace and defense-related applications.

The VU19P FPGA features 9 million system logic cells, up to 1.5 terabits per-second of DDR4 memory bandwidth and up to 4.5 terabits per-second of transceiver bandwidth, and over 2,000 user I/Os. It is 1.6X larger than its predecessor and what was previously the industry's largest FPGA — the 20 nm Virtex UltraScale 440 FPGA. 

"The VU19P enables developers to accelerate hardware validation and begin software integration before their ASIC or SoC is available," said Sumit Shah, senior director, product line marketing and management, Xilinx. "This is our third generation of world-record FPGAs. First was the Virtex-7 2000T, followed by the Virtex UltraScale VU440, and now the Virtex UltraScale+ VU19P. But this is more than silicon technology; we're providing robust and proven tool flows and IP to support it."

"Arm relies on Xilinx devices as part of our process for validating our next-generation processor IP and SoC technology," said Tran Nguyen, director of design services, Arm. "The new VU19P will further enable Arm, and many others in our ecosystem, to accelerate the design, development and validation of our most ambitious roadmap technologies."

The VU19P will be generally available in the fall of 2020.

https://www.xilinx.com/news/press/2019/xilinx-announces-the-world-s-largest-fpga-featuring-9-million-system-logic-cells.html

Monday, August 19, 2019

Cerebras Wafer Scale Engine packs 1.2 trillion transistors

Cerebras, a start-up based in Los Altos, California, unveiled its Wafer Scale Engine - a record-setting AI processor boasting a die size of 46,225 square millimeters and containing more than 1.2 trillion transistors. The chip is 56X larger than the largest graphics processing unit and contains 3,000X more on-chip memory.

Key specs

  • 400,000 Sparse Linear Algebra (SLA) cores
  • 18GB on-chip SRAM, all accessible within a single clock cycle, and provides 9 PB/s memory bandwidth. 
  • 100 Pb/s interconnect bandwidth in a 2D mesh
  • Manufactured by TSMC on its 16nm process technology

The SLAC cores are flexible, programmable, and optimized for the sparse linear algebra, which underpins neural network computation. The cores are linked together with a fine-grained, all-hardware, on-chip mesh-connected communication network called Swarm.

“Designed from the ground up for AI work, the Cerebras WSE contains fundamental innovations that advance the state-of-the-art by solving decades-old technical challenges that limited chip size—such as cross-reticle connectivity, yield, power delivery, and packaging,” said Andrew Feldman, founder and CEO of Cerebras Systems. “Every architectural decision was made to optimize performance for AI work. The result is that the Cerebras WSE delivers, depending on workload, hundreds or thousands of times the performance of existing solutions at a tiny fraction of the power draw and space.”

The Cerebras product unveiling occurred at this week's Hot Chips Conference at Stanford University.

http://www.cerebras.net

Tuesday, July 16, 2019

Alphawave intros PCIe Gen1 – Gen5 PHY

Alphawave IP introduced its PipeCORE PCIe Gen1-5 PHY, an advanced DSP based 7nm PCIe Gen1-5 PHY that is available on TSMC’s 7nm process technology.

The company says its PipeCORE can also demonstrate 64Gbps PAM4 rates for early PCI-Express Gen6 adopters.

The PipeCORE PHY leverages the same advanced high-speed ADC architecture utilized by Alphawave’s AlphaCORE Multi-Standard Serdes (MSS) IP that has been delivered to customers in 7nm since earlier in 2019.

“I am really proud that the Alphawave team has delivered working PCIe Gen1-5 silicon the first time!” said Tony Pialis, President and CEO of Alphawave.

https://awaveip.com/products/pipecore-gen1-5-phy/

Wednesday, July 10, 2019

Akash Systems raises $14.5 million for GaN-on-Diamond for sat comms

Akash Systems, a San Francisco-based startup focused on silicon for satellite communications, announced $14.5 million in Series A funding, including $10 million in new equity funds, and an additional $4.5 million converted from prior convertible notes.

Akash is currently manufacturing GaN-on-Diamond-based power amplifiers and radio modules for customers who make satellites requiring high frequency and high power efficiency. Its radio products are on track to hit the market in Q4 2019.

The company says it can achieve a dramatic reduction in the waste heat generated from the power amplifier by using GaN-on-Diamond technology, whereby the hottest part of a transistor is brought to within tens of nanometers of synthetic diamond – the most thermally conductive material developed to date.

Akash has designed its satellite transmit/receive radio modules to easily integrate with existing ground station and satellite infrastructure for satellite makers in all markets.

Investors in this round include Khosla Ventures, Founders Fund, ACME Capital, Sriram Krishnan, Correlation Ventures and others. Akash will deploy the new capital toward scaling its transmit/receive radio modules and power amplifier business, moving it closer to profitability.

“Akash Systems is playing a critical role in meeting the growing and vital need for improved satellite communications infrastructure,” said Delian Asparouhov of Founders Fund, which is focused on assisting entrepreneurs to build impactful new energy and technology companies. “We’re proud to be part of Akash’s journey as a critical enabler and accelerant in global communications.”

Monday, July 1, 2019

Applied Materials acquires Kokusai for batch wafer processing

Applied Materials agreed to acquire Kokusai Electric Corporation for $2.2 billion in cash from global investment firm KKR.

Kokusai Electric specializes in batch processing systems and services for memory, foundry and logic customers.

Applied said these systems complement its portfolio of single-wafer processing systems.

Following the close of the transaction, Kokusai Electric will operate as a business unit of Applied’s Semiconductor Products Group and continue to be based in Tokyo, with technology and manufacturing centers in Toyama, Japan and Cheonan, Korea. The acquisition is expected to be immediately accretive to Applied’s non-GAAP earnings per share at close.

“The opportunity to combine with Applied Materials will be very attractive for Kokusai Electric’s customers and employees alike,” said Fumiyuki Kanai, president and CEO of Kokusai Electric. “We are excited about the opportunity to integrate Kokusai Electric’s experienced team with Applied’s global development, customer support and services capabilities. We believe the combination will accelerate our ability to bring exciting new technologies to customers.”

http://www.appliedmaterials.com


Wednesday, June 26, 2019

European Commission opens investigation into Broadcom

The European Commission opened a formal antitrust investigation to assess whether Broadcom may be restricting competition through exclusivity practices with its set-top box and modem chipsets.

The Commission said it believes that Broadcom may be implementing a range of exclusionary practices, including (i) setting exclusive purchasing obligations, (ii) granting rebates or other advantages conditioned on exclusivity or minimum purchase requirements, (iii) product bundling, (iv) abusive IP-related strategies and (v) deliberately degrading interoperability between Broadcom products and other products.

EU law prohibits the abuse of a dominant market position to affect trade within the EU and prevent or restrict competition.

Margrethe Vestager, Commissioner in charge of competition policy, said "We suspect that Broadcom, a major supplier of components for these devices, has put in place contractual restrictions to exclude its competitors from the market. This would prevent Broadcom's customers and, ultimately, final consumers from reaping the benefits of choice and innovation. We also intend to order Broadcom to halt its behaviour while our investigation proceeds, to avoid any risk of serious and irreparable harm to competition."

http://europa.eu/rapid/press-release_IP-19-3410_en.htm

Thursday, May 30, 2019

Analog Devices debuts mmWave 5G chipset

Analog Devices (ADI) that combines ADI’s advanced beamformer IC, up/down frequency conversion (UDC), and additional mixed signal circuitry. This optimized “Beams to Bits” signal chain represents a unique set of capabilities only available from ADI.

The new mmWave 5G chipset includes the 16-channel ADMV4821 dual/single polarization beamformer IC, 16-channel ADMV4801 single-polarization beamformer IC and the ADMV1017 mmWave UDC. The 24- to 30-GHz beamforming + UDC solution forms a 3GPP 5G NR compliant mmWave front-end to address the n261, n257 and n258 bands. The high channel density, coupled with the ability to support both single- and dual-polarization deployments, greatly increases system flexibility and reconfigurability for multiple 5G use cases while best-in-class equivalent isotropically radiated power (EIRP) extends radio range and density.

“Millimeter-wave 5G is an emerging technology with great potential,” said Karim Hamed, general manager of Microwave Communications at Analog Devices. “It can be extremely difficult to design these systems from the ground up, balancing system-level challenges in performance, standards, and cost. This new solution leverages ADI’s best-in-class technology, long legacy in RF, microwave and mmWave communications infrastructure, and deep expertise across the RF spectrum to simplify the design process for customers, reduce overall component count, and accelerate the path to 5G deployment.”

http://www.analog.com

Monday, May 27, 2019

Innovium showcases switching silicon at Computex Taipei

At this week's Computex 2019 in Taipei, Innovium is showcasing its 12.8Tbps TERALYNX Ethernet switching technology.

Demonstrations will include interoperability with a broad range of 100-400G optics, DAC, ACC, re-timer/gearbox, and comprehensive software and SDK, including integration with latest and highly robust Software for Open Networking in the Cloud (SONiC) software.

https://www.innovium.com

Tuesday, May 14, 2019

Samsung charts progress from 10nm to 3mm Gate-All-Around

Samsung Electronics is making rapid progress in 3nm Gate-All-Around (GAA) process technology, which could see first tape out in 2021 and mass market production as early as 2022.

Compared to 7nm technology, Samsung’s 3GAE process aims to deliver a 45% reduction in chip area with 50% percent lower power consumption, and 35% higher performance, potentially benefiting applications as diverse as mobile, network, automotive, Artificial Intelligence (AI) and IoT.   Samsung's GAA MBCFET (Multi-Bridge-Channel FET) uses a nanosheet architecture, enabling greater current per stack. WhileFinFET structures must modulate the number of fins in a discrete way, MBCFET™provides greater design flexibility by controlling the nanosheet width.

At Samsung Foundry Forum event in Santa Clara California, company executives outlined the fabrication roadmap from today's 10nm down to 3nm. Some highlights:
  • 14/10nm - these are in high volume manufacturing. These will remain long-lasting technologies into the future
  • 8nm - the most advanced non-EUV technology
  • 7nm FinFET - currently under mass production for mobile applications. The first tape out was in 2018. IP re-use is supported.
  • 6nm FinFET -- mass production of 6nm process devices in the second half of 2019
  • 5nm FinFET - the product design of Samsung’s 5nm FinFET process, which was developed in April, is expected to be completed in the second half of this year and go under mass production in the first half of 2020
  • 4nm FinFET - will represent the maximum scaling of the 7nm family, and development will be completed later this year - 
  • 3nm Gate-All-Around (GAA) process development is on track and will leverage MBCFET (Multi-Bridge-Channel FET) based on nanosheet technology. A Process Design Kit (PDK) version 0.1 for 3GAE was released in April. This will be the future beyond FinFET.
“We stand at the verge of the Fourth Industrial Revolution, a new era of high-performance computing and connectivity that will advance the daily lives of everyone on the planet,” said Dr. ES Jung, President and head of Foundry Business at Samsung Electronics. “Samsung Electronics fully understands that achieving powerful and reliable silicon solutions requires not only the most advanced manufacturing and packaging processes as well as design solutions, but also collaborative foundry-customer relationships grounded on trust and shared vision. This year’s Foundry Forum is filled with compelling evidence of our commitment to progress in all those areas, and we’re honored to host and converse with our industry’s best and brightest,” Dr. Jung added.

Monday, April 22, 2019

Cadence says ready for TSMC’s 5nm FinFET

Cadence Design Systems confirmed that its digital, signoff and custom/analog tools have been certified for Design Rule Manual (DRM) and SPICE v1.0, and Cadence IP has been enabled for the TSMC 5nm process. The corresponding process design kits (PDKs) featuring integrated tools, flows and methodologies are now available for traditional and cloud-based environments. Additionally, mutual customers have already completed several tapeouts using Cadence tools, flows and IP for full production development on the TSMC 5nm process technology.

Cadence said it has delivered a fully integrated digital implementation and signoff tool flow, which has been certified on TSMC’s 5nm process that has the benefits of process simplification provided by extreme ultraviolet (EUV) lithography. The Cadence full-flow includes the Innovus Implementation System, Liberate Characterization Portfolio, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Pegasus™ Verification System.

“We’re continuing to broaden our collaboration with TSMC to facilitate 5nm FinFET adoption, giving customers access to the latest tools and IP for advanced process design creation,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Our R&D team has focused heavily on developing new features and performance improvements so that our digital and signoff and custom/analog tools and IP can be used with complete confidence, enabling customers to achieve first-pass silicon success and deliver end products within aggressive time-to-market schedules.”

http://www.cadence.com/go/tsmc5nmca


See also