Showing posts with label Silicon. Show all posts
Showing posts with label Silicon. Show all posts

Wednesday, October 13, 2021

Hailo raises $136 million for its edge AI processors

Hailo, a start-up based in Tel Aviv, raised $136 million in a Series C round of funding for its edge processor designed for AI workloads.

The Hailo-8 edge AI processor boasts up to 26 tera-operations per second (TOPS) performance, capable of processing of FHD stream in real-time, and with typical power consumption of 2.5W, according to the company.

The funding round was led by Poalim Equity and Gil Agmon with participation from existing investors including Hailo Chairman Zohar Zisapel, ABB Technology Ventures (ATV), Latitude Ventures and OurCrowd; and new investors Carasso Motors, Comasco, Shlomo Group, Talcar Corporation Ltd. and Automotive Equipment (AEV).

Hailo was established in Israel in 2017 by members of the Israel Defense Forces’ elite technology unit.

https://hailo.ai/

Wednesday, October 6, 2021

Samsung Foundry targets 3nm in 2022, 2nm in 2025

Samsung Foundry is scheduled to start producing its customers' first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023.

During its 5th annual Samsung Foundry Forum (SFF) 2021 underway this week, Samsung Electronics unveiled plans for continuous process technology migration to 3- and 2-nm based on the company’s Gate-All-Around (GAA) transistor structure.

Samsung said its first 3nm GAA process node utilizing Multi-Bridge-Channel FET (MBCFETTM) will allow up to 35 percent decrease in area, 30 percent higher performance or 50 percent lower power consumption compared to the 5nm process. In addition to power, performance, and area (PPA) improvements, as its process maturity has increased, 3nm’s logic yield is approaching a similar level to the 4nm process, which is currently in mass production.

The 2nm process node with MBCFET is in the early stages of development with mass production in 2025.

“We will increase our overall production capacity and lead the most advanced technologies while taking silicon scaling a step further and continuing technological innovation by application,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics. "Amid further digitalization prompted by the COVID-19 pandemic, our customers and partners will discover the limitless potential of silicon implementation for delivering the right technology at the right time."

Additionally, Samsung is advancing its 14nm process in order to support 3.3V high voltage or flash-type embedded MRAM (eMRAM) which enables increased write speed and density. It will be a great option for applications such as micro controller unit (MCU), IoT and wearables. Samsung’s 8nm radio frequency (RF) platform is expected to expand the company’s leadership in the 5G semiconductor market from sub-6GHz to mmWave applications.

http://news.samsung.com

Cadence debuts 3D-IC for multi-chiplet and advanced packaging

Cadence Design Systems released its Integrity 3D-IC platform integrating 3D chip design planning, implementation and system analysis.

Cadence says its platform provides system planning, integrated electrothermal, static timing analysis (STA) and physical verification flows, enabling faster, high-quality 3D design closure. It also incorporates 3D exploration flows, which take 2D design netlists to create multiple 3D stacking scenarios based on user input, automatically selecting the optimal, final 3D stacked configuration. 

Features and benefits:

  • Common cockpit and database: Lets SoC and package design teams co-optimize the system concurrently, allowing system-level feedback to be incorporated efficiently.
  • Complete planning system: Incorporates a 3D-IC stack planning system for all types of 3D designs, enabling customers to manage and implement native 3D stacking.
  • Seamless implementation tool integration: Provides ease of use through direct script-based integration with the Cadence Innovus Implementation System for high-capacity digital designs with 3D die partitioning, optimization and timing flows.
  • Integrated system-level analysis capabilities: Enables 3D-IC design through early electrothermal and cross-die STA, which allows early system-level feedback for system-driven PPA.
  • Co-design with the Virtuoso Design Environment and Allegro packaging technologies: Allows engineers to seamlessly move design data from Cadence analog and packaging environments to different parts of the system through the hierarchical database, enabling faster design closure and improved productivity.

“Cadence has historically offered customers strong 3D-IC packaging solutions through its leading digital, analog and package implementation product lines,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “With recent developments in advanced packaging technologies, we saw a need to further build upon our successful 3D-IC foundation, providing a more tightly integrated platform that ties our implementation technology with system-level planning and analysis. As the industry continues to move toward different configurations of 3D stacked dies, the new Integrity 3D-IC platform lets customers achieve system-driven PPA, reduced design complexity and faster time to market.”

http://www.cadence.com/go/3DIC


Tuesday, October 5, 2021

Marvell looks to TSMC's 3nm for custom ASICs

Marvell will use TSMC’s 3nm process technology to offer custom silicon for cloud data center, 5G carrier, automotive and enterprise markets.

Marvell is first to introduce a silicon platform that leverages 3nm process technology, advanced die-to-die interface IP, and TSMC’s advanced 2.5D Chip-on-Wafer-on-Substrate (CoWoS) packaging technology.

“Marvell is proud to be the lead ve3nm3nmndor to offer a 3nm platform for cloud-optimized solutions,” said Sandeep Bharathi, Executive Vice President, Central Engineering, System-on-Chip Group at Marvell. “Our new advanced node platform places Marvell on the leading edge of technology readiness with early Si validation of critical IPs to enable fast time-to-market.”

Marvell's new 3nm multi-chip platform includes two complementary advanced die-to-die interfaces. The first is a flexible extra short reach (XSR) interface for connecting multiple die on a package substrate for applications, like co-packaged optics (CPO) for cloud data centers. 

To address the growing needs for cloud-optimized silicon solutions from leading data center operators, Marvell is also developing an ultra-low power and low-latency parallel die-to-die interface with the highest bandwidth density in the industry. Compatible with emerging Open Compute Project (OCP) standards, the new parallel interface enables high-performance chiplet solutions by connecting multiple silicon devices on an interposer. Both interfaces are also available in 5nm to enable multi-node solutions.

The new platform also incorporates TSMC’s advanced CoWoS packaging technology, empowering continued data infrastructure performance scaling. Marvell said its collaboration with TSMC on CoWoS allows customers to build high-performance solutions for "the most demanding cloud data center applications."

https://www.marvell.com/products/custom-asic.html  


  • Earlier this year, TSMC stated that its 3nm technology (N3) will offer up to 70% logic density gain, up to 15% speed improvement at the same power and up to 30% power reduction at the same speed as compared with N5 technology. N3 is expected to receive multiple customer product tape-outs in 2021. In addition, volume production is targeted in second half of 2022.

Marvell debuts 5nm Prestera switch and 5nm OCTEON 10 5nm DPU

Marvell announced the availability of its 5nm Prestera DX 7321 Ethernet switch, the industry’s first 5nm 50G PAM4 device for the carrier market.

The new Marvell Prestera switch is designed for 5G fronthaul and edge applications. With the addition of the 5nm Prestera device, Marvell's carrier-optimized switch portfolio now comprises four Ethernet switches that scale port speeds from 1Gbps to 400Gbps with aggregate bandwidths ranging from 200Gbps to 1.6Tbps. 

Marvell also announced sampling of its 5nm OCTEON 10 DPU family, which will include hardware accelerators to address workloads required by 5G, cloud, carrier and enterprise data center applications. OCTEON 10 offers a mix of compute, hardware acceleration, data path bandwidth, and I/O including PCIe 5.0 and DDR5. 

Marvell’s 5G network solutions also include Alaska Ethernet PHYs and a broad portfolio of optical solutions for edge, metro and long-haul applications. In addition, Marvell’s COLORZ II 400ZR/ZR+ coherent optical modules are enabling carriers with high-capacity, long-reach DWDM connectivity directly from Ethernet switches.

“Carriers are requiring optimized high-performance, low-power and secured next-generation 5G data infrastructure solutions that enable new high-value applications,” said Raghib Hussain, president, Products and Technologies at Marvell. “Our 5nm switch and DPU set a new bar for power, performance and footprint, providing the breakthrough technology needed to fulfill the potential of 5G.”

https://www.marvell.com/

Monday, September 27, 2021

Astera raises $50 million for data center connectivity silicon

Astera Labs, a start-up based in Santa Clara, California, raised $50 million in an over subscribed Series-C funding round for its silicon solutions for intelligent systems.

Astera Labs recently launched its Aries Smart Retimer portfolio for Compute Express Link (CXL) 2.0 and PCI Express (PCIe) 5.0 that enable workload-optimized platforms in the cloud. The company is also developing ASIC and module solutions that unlock complex system topologies critical to mainstreaming data-intensive applications such as Artificial Intelligence and Machine Learning.

The new funding was led by Fidelity Management and Research. Fidelity was joined in this funding round by Atreides Management and Valor Equity Partners, with continued participation from existing investors Avigdor Willenz Group, GlobalLink1 Capital, Intel Capital, Sutter Hill Ventures, and VentureTech Alliance. Prior to this round, Astera Labs raised only $35 million over three years.

“We are thrilled to join forces with Fidelity, Atreides, and Valor to cement our leadership position in intelligent cloud connectivity solutions and usher Astera Labs into the next growth phase of our company,” said Jitendra Mohan, CEO, Astera Labs. “With this investment and increased collaboration with our manufacturing partners, we will rapidly scale our worldwide operations to satisfy incredible customer demand and launch multiple new product lines to solve the industry’s most pressing connectivity challenges.”

“CXL has opened a new era of data center system architecture that is critical to realize the vision of AI in the cloud,” said Sanjay Gajendra, Chief Business Officer, Astera Labs. “We are leading the industry with design wins at the five most significant CPU/GPU/AI processor platforms in the world and the majority of Cloud customers. This positions us well to capitalize on CXL’s exciting new capabilities for cache-coherent and memory interconnects.”

http://www.AsteraLabs.com

Friday, September 24, 2021

Intel breaks ground on $20 billion fabs in AZ

Intel broke ground on two new fabs (52 and 62) at the company’s Ocotillo campus in Chandler, Arizona. When fully operational in 2024, the new fabs will manufacture Intel’s most advanced process technologies, including Intel 20A featuring the new RibbonFET and PowerVia innovations. The capacity is expected to be used for Intel's own products as well as for customers of the newly formed Intel Foundry Services.

“Today’s celebration marks an important milestone as we work to boost capacity and meet the incredible demand for semiconductors: the foundational technology for the digitization of everything. We are ushering in a new era of innovation – for Intel, for Arizona and for the world. This $20 billion expansion will bring our total investment in Arizona to more than $50 billion since opening the site over 40 years ago. As the only U.S.-based leading-edge chipmaker, we are committed to building on this long-term investment and helping the United States regain semiconductor leadership,” stated Pat Gelsinger, Intel CEO.



Tuesday, September 21, 2021

Nokia launches its FP5 network processing silicon

Nokia unveiled its fifth-generation FP5 IP routing silicon capable of powering 800GE routing interfaces in service provider networks. Nokia promises a 75% reduction in power consumption and new embedded line rate, flow-based encryption capabilities.  FP5-based platforms will be available starting in the first half of 2022.

Nokia's FP5 is a fully programmable network processor (NPU) for Nokia’s IP service routing platforms. The company says the FP5 is the first ASIC on the market to deliver up to 48 ports of QSFP-DD 800 without further hardware or fabric upgrades. Some highlights:

Security: With the current generation FP4 silicon, Nokia transformed volumetric DDoS defense with router-based detection and mitigation. With FP5, Nokia brings an additional layer of network protection with the introduction of ‘ANYsec’ - a new line rate, flow-based encryption capability integrated directly into the chipset. ANYsec supports the delivery of secure IP services including MPLS and segment routing, on-demand and at scale without impacting performance or power efficiency. Service providers can now ensure the integrity and confidentiality of all data flowing through their networks.

Network Capacity. Nokia service router platforms are the first to support high-density 800GE and 1.6 Tbps clear channel routing interfaces for applications including mobile transport, IP core, peering, BNG and provider edge. New FP5-based line cards will support 14.4 Tbps (19.2 Tbps with Nokia’s intelligent aggregation capability.) A new series of fixed form factor 7750 Service Router-1 platforms enable the benefits of FP5 to also be realized in smaller network locations.

Energy Efficiency: Nokia’s FP5 network processors drive down power consumption per bit by 75%. As FP5 is backwards compatible with FP4 and fully integrated into the latest versions of Nokia’s Service Router Operating System (SR OS), all existing features are supported from day one on the new hardware. 

Some specs:

  • 4.8 Tbps
  • delivered with a 2.5D system-in-package (SiP) construct
  • First NPU to support 100G SERDES
  • Largest device in the industry using line rate memories everywhere, for both buffering and tables, in a completely deterministic configuration
  • First NPU with embedded line-rate network encryption for L2, L2.5 and L3
  • First to support multiple 1.6 Tbps clear channel flows
  • Support for 400G ZR/ZR+, 800G and 1.6 Tbps speeds
  • External MAC ASIC with QoS pre-processing, pre-classification, pre-buffering and first level DDoS protection and encryption

Federico GuillĂ©n, President of Network Infrastructure, Nokia, said: “Of all the things that are surprising about human beings, perhaps the most surprising is our ability to be surprised. Our customers require their networks to be robust, agile and adaptable enough to handle everything life throws at them – from disruptive security threats to a global pandemic. FP5 is a significant step forward in performance, security and efficiency and – in combination with our software excellence and investment in network automation and tools – it opens the next chapter in Nokia’s long-standing leadership in IP networking and IP silicon innovation.”

Neil McRae, Managing Director and Chief Architect, BT, said: “BT has a long-standing relationship with Nokia, and we are pleased to see that with FP5, Nokia continues to innovate to ensure IP networks have the scale, flexibility and features to help us stay ahead of escalating demand from our residential, mobile and business customers. In particular, we are very happy to see the focus on power optimization as we grow our network, with both BT and Nokia committing to significant reduction in carbon footprint. In the past 18 months, our lives have been turned upside down, and our reliance on networks has been dramatically increased and reliability for customers is crucially important. With security being ever more important for our customers, seeing Nokia’s approach to building more security features into the platform is fantastic.”

Nokia – IP networks re-imagined

Recently we have seen Cisco predict that busy hour global IP traffic will grow 4.6-fold (35% CAGR) from 2016 to 2021, reaching 4.3 Pb/s by 2021, compared to average Internet traffic that will grow 3.2-fold (26% CAGR) over the same period to reach 717 Tb/s by 2021. The latest edition of the Ericsson Mobility Report, released earlier this week, calculates that the total traffic in mobile networks increased by 70% between the end of Q1 2016 and the...

Nokia Unveils its Next Gen IP Routing Engine

Nokia unveils its fourth generation network processing silicon for powering the first petabit-class core IP routers. The new FP4 silicon, which comes six years after the preceding FP3 chipset was announced, offers 2.4 Tb/s half-duplex capacity, or 6X more capacity than the current generation 400 Gb/s FP3 chipset. The FP4 will support full terabit IP flows. All conventional routing capabilities are included. Deep classification capabilities include...

Tuesday, September 14, 2021

Gigaphoton to double production of excimer laser light sources


Gigaphoton, a manufacturer of light sources used in semiconductor lithography, announced plans to double its production capacity of excimer laser light sources by 2023. The company is constructing a new facility, with its doors to open in April 2022, in order to establish a more stable supply system. 

Katsumi Uranaka, President & CEO of Gigaphoton said, “With demand for semiconductors on the rise around the world, we will do our utmost to meet the demand from our customers. This fiscal year, we will make full use of our existing resources for production and improve the efficiency of our production planning and lead times. Next year, the new facility will be completed and we will have a more stable supply system in place. As a manufacturer of lithography light sources, which are essential for semiconductor manufacturing, we will continue to contribute to the industrial sector by supporting the supply and operation of our products in a responsible manner.”

https://www.gigaphoton.com/en/


Tuesday, September 7, 2021

Intel eyes automotive silicon expansion

Intel CEO Pat Gelsinger predicts the “digitization of everything” will push the share of semiconductors in the total new premium vehicle bill of materials (BOM) to more than 20% by 2030 – up more than 5X from 4% in 2019. The company forecasts the total addressable market (TAM) for automotive silicon will more than double by the end of the decade to $115 billion – approximately 11% of the entire silicon market.2

In pursuit of this opportunity, Intel announced plans to build new chip manufacturing facilities in Europe, establish committed foundry capacity at its Ireland site, and launch the Intel Foundry Services Accelerator to help foundry customers move automotive designs to advanced nodes.

In addition, Intel's Mobileye division unveiled the first production AV equipped with the Mobileye Drive self-driving system and bearing the MoovitAV services branding. Mobileye is working with Sixt to bring autonomous ride-hailing into operation with Munich-based Sixt SE starting in 2022. 


https://www.intel.com/

Tuesday, August 31, 2021

Semtech ships its 50G PAM4 CDR chipset

Semtech’s newest Tri-Edge clock and data recovery (CDR) chipset, which targets data center interconnectivity over multi-mode fiber, has entered into full production status.

The Semtech GN2538 is a dual-channel 50G PAM4 CDR with integrated VCSEL drivers and the GN2539 is a dual-channel 50G PAM4 CDR with integrated linear transimpedence amplifiers (TIAs). This chipset is the latest addition to the proven Tri-Edge CDR platform, and the low power and ease of implementation of the GN2538 and GN2539 will allow major data centers to upgrade their intra-data center interconnects and enhance overall performance.

The laser driver integrated in the GN2538 includes proprietary VCSEL compensation to enable a wide range of VCSEL options with fully adaptive input equalization and easy startup to streamline system bring up. The integrated linear TIA in the GN2559 provides superior receiver performance with reliable adaptation and includes configurable output de-emphasis enabling robust and compliant electrical interfaces.

“Our customers have fully tested the solutions confirming interoperability with 100G ports of commercial Ethernet switches used in major data centers. The integration offered by the analog PAM4 GN2538 and GN2539 chipset enables reduced cost, and delivers the highly desired low power and low latency performance that meets the needs of high-performance computing (HPC), artificial intelligence (AI) and Cloud data center networks. This chipset is also fully compliant to the 50G per lane multi-mode fiber Open Eye MSA specification,” said Julius Yam, market manager, Data Center Products in Semtech’s Signal Integrity Products Group.

http://www.semtech.com/optical

Monday, August 30, 2021

Renesas completes acquisition of Dialog Semi

Renesas Electronics completed its previously announced acquisition of Dialog Semiconductor Plc.  Renesas will fund the cash consideration payable to Dialog shareholders of approximately EUR 4.8 billion (approximately 624.0 billion yen at an exchange rate of 130 yen to the Euro) through a combination of debt, cash on hand and the proceeds of an equity offering of approximately 222.6 billion yen 

Dialog, which is based in Reading, UK, is provider of highly-integrated and power-efficient mixed-signal ICs used in IoT, consumer electronics and high-growth segments of automotive and industrial end-markets. Dialog brings a wide range of product offerings including battery and power management, power conversion, configurable mixed-signal (CMIC), LED drivers, custom mixed-signal ICs (ASICs), and automotive power management ICs (PMICs), wireless charging technology, and more. Dialog also offers broad and differentiated BLE, WiFi and audio system-on-chips (SoCs) that deliver advanced connectivity for a wide range of applications; from smart home/building automation, wearables, to connected medical. All these systems complement and expand Renesas’ leadership portfolio in delivering comprehensive solutions to improve performance and efficiency in high-computing electronic systems. Dialog was founded in 1981 and has 2,300 employees.

“Today represents an important milestone for Renesas. This transaction builds on our long-term strategy to offer a complete set of solutions with more leading-edge analog and mixed signal products that deliver value and innovation to the customers,” said Hidetoshi Shibata, President & CEO of Renesas. 



https://www.renesas.com/br/en/document/ppt/renesas-and-dialog-zoom-webinar-presentation-material


Renesas to acquire Integrated Device Technology for $6.7 billion

Renesas Electronics Corporation of Japan has agreed to acquire Integrated Device Technology (IDT, NASDAQ: IDTI) for approximately US$6.7 billion (approximately 733.0 billion yen at an exchange rate of 110 yen to the dollar), combing two recognized leaders in embedded processors and analog mixed-signal semiconductors. IDT shares are to be acquired at a price of US$49.00 per share. IDT, which is based in San Jose, California, is a leading supplier...

Renesas Electronics Corporation agreed to acquire Intersil for US$22.50 per share in cash, representing an aggregate equity value of approximately US$3.2 billion (approximately 321.9 billion yen at an exchange rate of 100 yen to the dollar). Renesas supplies microcontroller (MCU) and system-on-chip (SoC) products and technologies.  Intersil specializes in power management and precision analog capabilities. The acquisition is also expected...

Tuesday, August 24, 2021

Cerebras advances its "Brain-scale AI"

Cerebras Systems disclosed progress in its mission to deliver a "brain-scale" AI solution capable of supporting neural network models of over 120 trillion parameters in size. 

Cerebras’ new technology portfolio contains four innovations: Cerebras Weight Streaming, a new software execution architecture; Cerebras MemoryX, a memory extension technology; Cerebras SwarmX, a high-performance interconnect fabric technology; and Selectable Sparsity, a dynamic sparsity harvesting technology.

  • Cerebras Weight Streaming enables the ability to store model parameters off-chip while delivering the same training and inference performance as if they were on chip. This new execution model disaggregates compute and parameter storage – allowing researchers to flexibly scale size and speed independently – and eliminates the latency and memory bandwidth issues that challenge large clusters of small processors. It is designed to scale from 1 to up to 192 CS-2s with no software changes.
  • Cerebras MemoryX is a memory extension technology. MemoryX will provide the second-generation Cerebras Wafer Scale Engine (WSE-2) up to 2.4 Petabytes of high performance memory, all of which behaves as if it were on-chip. With MemoryX, CS-2 can support models with up to 120 trillion parameters.
  • Cerebras SwarmX is a high-performance, AI-optimized communication fabric that extends the Cerebras Swarm on-chip fabric to off-chip. SwarmX is designed to enable Cerebras to connect up to 163 million AI optimized cores across up to 192 CS-2s, working in concert to train a single neural network.
  • Selectable Sparsity enables users to select the level of weight sparsity in their model and provides a direct reduction in FLOPs and time-to-solution. Weight sparsity is an exciting area of ML research that has been challenging to study as it is extremely inefficient on graphics processing units. Selectable sparsity enables the CS-2 to accelerate work and use every available type of sparsity—including unstructured and dynamic weight sparsity—to produce answers in less time.

“Today, Cerebras moved the industry forward by increasing the size of the largest networks possible by 100 times,” said Andrew Feldman, CEO and co-founder of Cerebras. “Larger networks, such as GPT-3, have already transformed the natural language processing (NLP) landscape, making possible what was previously unimaginable. The industry is moving past 1 trillion parameter models, and we are extending that boundary by two orders of magnitude, enabling brain-scale neural networks with 120 trillion parameters.”

https://cerebras.net/news/cerebras-systems-announces-worlds-first-brain-scale-artificial-intelligence-solution/


Cerebras unveils 2nd-gen, 7nm Wafer Scale Engine chip

Cerebras Systems introduced its Wafer Scale Engine 2 (WSE-2) AI processor, boasting 2.6 trillion transistors and 850,000 AI optimized cores.

The wafer-sized processor, which is manufactured by TSMC on its 7nm-node, more than doubles all performance characteristics on the chip - the transistor count, core count, memory, memory bandwidth and fabric bandwidth - over the first generation WSE. 

“Less than two years ago, Cerebras revolutionized the industry with the introduction of WSE, the world’s first wafer scale processor,” said Dhiraj Mallik, Vice President Hardware Engineering, Cerebras Systems. “In AI compute, big chips are king, as they process information more quickly, producing answers in less time – and time is the enemy of progress in AI. The WSE-2 solves this major challenge as the industry’s fastest and largest AI processor ever made.”


The processors powers the Cerebras CS-2 system, which the company says delivers hundreds or thousands of times more performance than legacy alternatives, replacing clusters of hundreds or thousands of graphics processing units (GPUs) that consume dozens of racks, use hundreds of kilowatts of power, and take months to configure and program. The CS-2 fits in one-third of a standard data center rack.

Early deployment sites for the first generation Cerebras WSE and CS-1 included Argonne National Laboratory, Lawrence Livermore National Laboratory, Pittsburgh Supercomputing Center (PSC) for its groundbreaking Neocortex AI supercomputer, EPCC, the supercomputing centre at the University of Edinburgh, pharmaceutical leader GlaxoSmithKline, and Tokyo Electron Devices, amongst others.

“At GSK we are applying machine learning to make better predictions in drug discovery, so we are amassing data – faster than ever before – to help better understand disease and increase success rates,” said Kim Branson, SVP, AI/ML, GlaxoSmithKline. “Last year we generated more data in three months than in our entire 300-year history. With the Cerebras CS-1, we have been able to increase the complexity of the encoder models that we can generate, while decreasing their training time by 80x. We eagerly await the delivery of the CS-2 with its improved capabilities so we can further accelerate our AI efforts and, ultimately, help more patients.”

“As an early customer of Cerebras solutions, we have experienced performance gains that have greatly accelerated our scientific and medical AI research,” said Rick Stevens, Argonne National Laboratory Associate Laboratory Director for Computing, Environment and Life Sciences. “The CS-1 allowed us to reduce the experiment turnaround time on our cancer prediction models by 300x over initial estimates, ultimately enabling us to explore questions that previously would have taken years, in mere months. We look forward to seeing what the CS-2 will be able to do with more than double that performance.”

https://cerebras.net/product

Monday, August 23, 2021

IBM Telum Processor features interconnect to link up to 32 chips

IBM unveiled its upcoming Telum Processor for artificial intelligence applications. A Telum-based system is planned for the first half of 2022.

Telum is IBM's first processor that contains on-chip acceleration for AI inferencing while a transaction is taking place. The chip contains 8 processor cores with a deep super-scalar out-of-order instruction pipeline, running with more than 5GHz clock frequency, optimized for the demands of heterogenous enterprise class workloads. The completely redesigned cache and chip-interconnection infrastructure provides 32MB cache per core, and can scale to 32 Telum chips. The dual-chip module design contains 22 billion transistors and 19 miles of wire on 17 metal layers.

The chip is developed in Samsung's 7nm EUV technology node.

IBM said its Telum processor excels in AI-specific workloads, such financial services workloads like fraud detection, loan processing, clearing and settlement of trades, anti-money laundering and risk analysis. 

https://newsroom.ibm.com/2021-08-23-IBM-Unveils-On-Chip-Accelerated-Artificial-Intelligence-Processor

Intel secures foundry contract in Pentagon's RAMP-C program

The U.S. Department of Defense awarded Intel an agreement to provide commercial foundry services in the first phase of its multi-phase Rapid Assured Microelectronics Prototypes - Commercial (RAMP-C) program. 

The RAMP-C program was created to facilitate the use of a U.S.-based commercial semiconductor foundry ecosystem to fabricate the assured leading-edge custom and integrated circuits and commercial products required for critical Department of Defense systems. In October 2020, DOD launched the RAMP program using the Advanced Commercial Capabilities Project Phase 1 Other Transaction Authority. 

The contract was awarded to the newly established Intel Foundry Services business through the NSTXL consortium-based S2MARTS OTA. Financial terms were not disclosed.

“One of the most profound lessons of the past year is the strategic importance of semiconductors, and the value to the United States of having a strong domestic semiconductor industry. Intel is the sole American company both designing and manufacturing logic semiconductors at the leading edge of technology. When we launched Intel Foundry Services earlier this year, we were excited to have the opportunity to make our capabilities available to a wider range of partners, including in the U.S. government, and it is great to see that potential being fulfilled through programs like RAMP-C,” stated Pat Gelsinger, Intel CEO

Under RAMP-C Intel Foundry Services will partner with industry leaders, including IBM, Cadence, Synopsys and others, to support the U.S. government’s needs for designing and manufacturing assured integrated circuits by establishing and demonstrating a semiconductor IP ecosystem to develop and fabricate test chips on Intel 18A, Intel’s most advanced process technology.

“The RAMP-C program will enable both commercial foundry customers and the Department of Defense to take advantage of Intel’s significant investments in leading-edge process technologies,” said Randhir Thakur, Intel Foundry Services president. “Along with our customers and ecosystem partners, including IBM, Cadence, Synopsys and others, we will help bolster the domestic semiconductor supply chain and ensure the United States maintains leadership in both R&D and advanced manufacturing. We look forward to a long-term collaboration with the U.S. government as we deliver RAMP-C program milestones.”

https://www.intel.com/content/www/us/en/newsroom/news/intel-wins-us-project-develop-foundry-ecosystem.html 

U.S. DoD backs Intel for semiconductor packaging tech

The U.S. Department of Defense awarded a contract to Intel to enable the U.S. government to access Intel’s state-of-the-art semiconductor packaging capabilities in Arizona and Oregon.

The project, which is supported by the DoD's State-of-the-Art Heterogeneous Integration Prototype (SHIP) program,  is executed by the Naval Surface Warfare Center, Crane Division, and administered by the National Security Technology Accelerator.

The second phase of SHIP will develop prototypes of multichip packages and accelerate advancement of interface standards, protocols and security for heterogeneous systems. SHIP prototypes will integrate special-purpose government chips with Intel’s advanced, commercially available silicon products, including field programmable gate arrays, application-specific integrated circuits and CPUs. This combination of technologies provides new paths for the U.S. government’s industry partners to develop and modernize the government’s mission-critical systems while taking advantage of Intel’s U.S. manufacturing capabilities.

Heterogeneous packaging allows the assembly of multiple, separately manufactured integrated circuit dies (chips) onto a single package to increase performance while reducing power, size and weight. SHIP provides the U.S. government access to Intel’s advanced heterogeneous packaging technologies, including embedded multi-die interconnect bridge (EMIB), 3D Foveros and Co-EMIB (combining both EMIB and Foveros).

“Intel and the U.S. government share a priority to advance domestic semiconductor manufacturing technology. The SHIP program will enable the Department of Defense to take advantage of Intel’s advanced semiconductor packaging capabilities, diversifying their supply chain and protecting their intellectual property while also supporting ongoing semiconductor R&D in the U.S. and preserving critical capabilities onshore,” stated Jim Brinker, president and general manager of Intel Federal LLC.

“To ensure that the U.S. defense industry base can continue to deliver state-of-the-art electronics for national security, it is imperative that the Department of Defense (DoD) partners with leading U.S. semiconductor companies," Nicole Petta, principal director of microelectronics, Office of the Under Secretary of Defense for Research and Engineering. "The DoD microelectronics roadmap recognizes the importance of strategic partnerships with industry. The roadmap also prioritizes and recognizes that as process scaling slows, heterogeneous assembly technology is a critical investment for both the DoD and our nation. SHIP directly contributes to advancing the objectives outlined in the DoD roadmap and the DoD looks forward to working with Intel, a world leader in this technology.”

http://www.intel.com




In 2018, Intel demonstrated a new 3D packaging technology, called "Foveros," which for the first time brings 3D stacking to logic-on-logic integration. Foveros will will allow products to be broken up into smaller “chiplets,” where I/O, SRAM and power delivery circuits can be fabricated in a base die and high-performance logic chiplets are stacked on top. The first Foveros product will combine a high-performance 10nm compute-stacked chiplet with a low-power 22FFL base die. 

Wednesday, August 18, 2021

EdgeQ samples its RISC-V 5G base station-on-a-Chip

EdgeQ, a start-up based in Santa Clara, California, is now sampling its RISC-V based, 5G Base Station-on-a-Chip to customers developing enterprise-grade 5G access points, Open-Radio Access Network (O-RAN) based Radio Unit (RU) and Distributed Unit (DU).

The EdgeQ platform combines highly integrated silicon with up to 50 RISC-V cores and 5G PHY software for processing all key functionalities and critical algorithms of the radio access network such as beamforming, channel estimation, massive MIMO and interference cancellation. The design is programmable and provides an open framework for L2/L3 software partners. 

EdgeQ, which has been developing its platform for the past three years, said traditional merchant silicon vendors offer the PHY as a reference software, placing the development burden on customers to invest years of effort to operationalize into production. By abstracting this friction with a total platform solution including a production-readied 5G PHY software, EdgeQ frees customers from the substantial investments, resources and time typically associated with productizing the 4G/5G PHY stack.

“Since day one, EdgeQ has been relentless about redefining the consumption and deployment model of 5G with its RISC-V based open architecture that converges connectivity, networking, and compute. How we elegantly club the hardware, the deployable RAN software, and an innovative chipset-as-a-service business model all together is what crystallizes the vision in a disruptively compelling way,” said Vinay Ravuri, CEO and Founder, EdgeQ. “Our sampling announcement today signifies that all this is a market reality.”

http://www.edgeq.io

EdgeQ pursues a feature subscription model for 5G basestation chip

EdgeQ, a start-up offering a 5G systems-on-a-chip, introduced a 5G chipset-as-a-service model in which customers can scale 5G and AI features as a function of subscription payments.  The service-oriented model would enable customers to scale from nominal to advanced 5G features such as ultra-reliable low latency communications, geo-location services, massive MIMO, fine-grained network slicing, as well as extending compatibility to other legacy wireless protocols. 

The company says its new service model is the very first in the chip industry to scale price, performance, and features as a function of need and use.  The potential is to elevate 5G Open Radio Access network (O-RAN) to an even more configurable, elastic, open wireless infrastructure. Enterprise network, telco, and cloud providers might also use the EdgeQ model to virtualize network resources.

“Our vision at EdgeQ has always been about implementing 5G in a format that is accessible, consumable, and intuitive for our customers. EdgeQ is not only the first company to converge both 5G and AI on a single chip for wireless infrastructure, but we are also able to make those capabilities available in a SaaS model.  This fundamentally reduces the initial capex investment required for 5G, thereby removing both technical and economic barriers of 5G adaptation at greenfield enterprises,” said Vinay Ravuri, CEO and Founder, EdgeQ. “This pay-as-you-go model ensures that the evolving demands of the market can leverage the full fluidity and elasticity of EdgeQ’s 5G-as-a-Service product.”



https://edgeq.io/



Video: New Silicon and Open Software Driving a New Ecosystem

There’s a plethora of interest in the 5G space from operators to enterprises and cloud service providers. In this video, Vinay Ravuri, CEO and Founder of EdgeQ, talks about how box makers are transforming with the emerging 5G market and how open software is driving a new set of markets.

https://youtu.be/KyRgSlZBpQQ

Monday, August 2, 2021

Ampere to acquire OnSpecta for its inference software

Ampere has agreed to acquire OnSpecta, a start-up based Redwood City, California offering AI inference optimization software.  Financial terms were not disclosed.

OnSpecta claims its Deep Learning Software (DLS) AI optimization engine can deliver significant performance enhancements over commonly used CPU-based machine learning (ML) frameworks. The companies said they have already demonstrated over 4x acceleration on Ampere-based instances running popular AI-inference workloads. 


"We are excited to welcome the talented OnSpecta team to Ampere," said Renee James, founder, chairman and CEO of Ampere Computing.  " The addition of deep learning expertise will enable Ampere  to deliver a more robust platform for inference task processing with lower power, higher performance and better predictability than ever. This acquisition underscores our commitment to delivering a truly differentiated cloud native computing platform for our customers in both cloud and edge deployments."


Saturday, July 31, 2021

Microchip announces network synchronization platform

Microchip Technology Inc. introduced a single-chip, highly integrated, low-power, multi-channel integrated circuit (IC) that can be coupled with the company’s IEEE 1588 Precision Time Protocol (PTP) and clock recovery algorithm software modules.

“Our newest ZL3073x/63x/64x network synchronization platform implements sophisticated measure, calibrate and tune capabilities, thereby significantly reducing network equipment time error to meet the most stringent 5G requirements,” said Rami Kanama, vice president of Microchip’s timing and communications business unit. “A uniquely flexible architecture for implementing the necessary channel density as well as high-performance, low-jitter synthesizers help simplify the design of timing cards, line cards, Radio Units (RU), Centralized Units (CUs) and Distributed Units (DUs) for 5G Radio Access Networks (RAN).”

Microchip said its measure, calibrate and tune capabilities ensure 5G systems achieve International Telecommunication Union – Telecommunication (ITU-T) Standard G.8273.2 Class C (30ns max|TE|) and the emerging Class D (5ns max|TEL|) time error requirements. The architecture provides flexibility, offering up to five independent Digital Phase Locked Loop (DPLL) channels while consuming only 0.9W of power in a compact 9 x 9-millimeter package that simultaneously reduces board space, power and system complexity.

With five ultra-low-jitter synthesizers, this latest platform offers 100 femtosecond (fs) root mean square (rms) jitter performance required by high-speed interfaces in the latest 5G RU, DU and CU systems.

Microchip’s network synchronization platform software includes its ZLS30730 high-performance algorithm coupled with its ZLS30390 IEEE 1588-2008 protocol engine. Both are widely deployed in 3G, 4G and 5G networks with precise timing capabilities.

Microchip’s ZL3073x/63x/64x network synchronization platform combines seamlessly with the company’s family of precision 5G oscillators – for example, the OX-601 Oven Controlled Crystal Oscillator (OCXO) – to offer 5G network operators a total system solution.

The company’s extensive portfolio of timing and clock solutions include clock generation, fanout buffer and jitter attenuator solutions as well as quartz and MEMS oscillators is complemented by a broad family of Ethernet physical layer (PHY) devices.

Tuesday, July 27, 2021

Blaize raises $71 million in Series D for edge AI silicon

Blaize, a start-up based in El Dorado Hills, California, announced $71 million in Series D round of funding for its edge AI computing solutions in automotive, mobility, smart retail, security, industrial and metro market sectors.

The funding round was led by Franklin Templeton, a new investor, and Temasek, an existing investor, led the round, along with participation from DENSO and other new and existing investors.

“Blaize System on Chip (“SoCs”) for automotive edge and central compute functions are accelerating electric vehicles and future architectural ambitions of automotive OEMs,” said Tony Cannestra, Director of Corporate Ventures, DENSO. “With substantial power advantages making EVs more efficient and economical, Blaize SoCs offer best in class performance with lower power across in-cabin, out of vehicle, and autonomous operations, enabling a streamlined architectural evolution to centralize compute.”

http://www.blaize.com

Monday, July 26, 2021

Intel unveils RibbonFET transistor architecture

Intel unveiled RibbonFET, its first new transistor architecture in more than a decade, and PowerVia, a new backside power delivery method. 

In a webcast presentation highlighting its process and packaging technology roadmaps through 2025, Intel vowed a swift adoption of next-generation extreme ultraviolet lithography (EUV), referred to as High Numerical Aperture (High NA) EUV. The company said it is on-track to received the first High NA EUV production tool in the industry.

Intel's roadmap, with new node names, includes:

  • Intel 7 delivers an approximately 10% to 15% performance-per-watt increase versus Intel 10nm SuperFin, based on FinFET transistor optimizations. Intel 7 will be featured in products such as Alder Lake for client in 2021 and Sapphire Rapids for the data center, which is expected to be in production in the first quarter of 2022.
  • Intel 4 fully embraces EUV lithography to print incredibly small features using ultra-short wavelength light. With an approximately 20% performance-per-watt increase, along with area improvements, Intel 4 will be ready for production in the second half of 2022 for products shipping in 2023, including Meteor Lake for client and Granite Rapids for the data center.
  • Intel 3 leverages further FinFET optimizations and increased EUV to deliver an approximately 18% performance-per-watt increase over Intel 4, along with additional area improvements. Intel 3 will be ready to begin manufacturing products in the second half of 2023.
  • Intel 20A ushers in the angstrom era with two breakthrough technologies, RibbonFET and PowerVia. RibbonFET, Intel’s implementation of a gate-all-around transistor, will be the company’s first new transistor architecture since it pioneered FinFET in 2011. The technology delivers faster transistor switching speeds while achieving the same drive current as multiple fins in a smaller footprint. PowerVia is Intel’s unique industry-first implementation of backside power delivery, optimizing signal transmission by eliminating the need for power routing on the front side of the wafer. Intel 20A is expected to ramp in 2024. The company is also excited about the opportunity to partner with Qualcomm using its Intel 20A process technology.
  • 2025 and Beyond: Beyond Intel 20A, Intel 18A is already in development for early 2025 with refinements to RibbonFET that will deliver another major jump in transistor performance. Intel is also working to define, build and deploy next-generation High NA EUV, and expects to receive the first production tool in the industry. Intel is partnering closely with ASML to assure the success of this industry breakthrough beyond the current generation of EUV.

“Intel has a long history of foundational process innovations that have propelled the industry forward by leaps and bounds,” said Dr. Ann Kelleher, senior vice president and general manager of Technology Development. “We led the transition to strained silicon at 90nm, to high-k metal gates at 45nm and to FinFET at 22nm. Intel 20A will be another watershed moment in process technology with two groundbreaking innovations: RibbonFET and PowerVia.”

Regarding its packaging innovations, Intel provided the following updates:

  • Sapphire Rapids will be the first Intel Xeon data center product to ship in volume with EMIB (embedded multi-die interconnect bridge). It will also be the first dual-reticle-sized device in the industry, delivering nearly the same performance as a monolithic design. Beyond Sapphire Rapids, the next generation of EMIB will move from a 55-micron bump pitch to 45 microns.
  • Foveros leverages wafer-level packaging capabilities to provide a first-of-its-kind 3D stacking solution. Meteor Lake will be the second-generation implementation of Foveros in a client product and features a bump pitch of 36 microns, tiles spanning multiple technology nodes and a thermal design power range from 5 to 125W.
  • Foveros Omni ushers in the next generation of Foveros technology by providing unbounded flexibility with performance 3D stacking technology for die-to-die interconnect and modular designs. Foveros Omni allows die disaggregation, mixing multiple top die tiles with multiple base tiles across mixed fab nodes and is expected to be ready for volume manufacturing in 2023.
  • Foveros Direct moves to direct copper-to-copper bonding for low-resistance interconnects and blurs the boundary between where the wafer ends and where the package begins. Foveros Direct enables sub-10-micron bump pitches, providing an order of magnitude increase in the interconnect density for 3D stacking, opening new concepts for functional die partitioning that were previously unachievable. Foveros Direct is complementary to Foveros Omni and is also expected to be ready in 2023.

https://www.intc.com/news-events/press-releases/detail/1486/intel-accelerates-process-and-packaging-innovations