Showing posts with label Silicon. Show all posts
Showing posts with label Silicon. Show all posts

Wednesday, April 21, 2021

SiFive licenses its RISC-V core IP to Renesas

Renesas Electronics and SiFive agreed to jointly develop next-generation, high-end RISC-V solutions for automotive applications. The partnership will also include SiFive licensing the use of their RISC-V core IP portfolio to Renesas.

Renesas provides automotive solutions including ADAS, Autonomous Driving (AD), Electric Vehicles (EV), and Connected Gateway (CoGW) to customers all over the world.

The SiFive Intelligence platform, based on SiFive RISC-V Vector processors with AI ISA extensions, features a differentiated software toolchain to enable the development of scalable solutions for AI and ML applications. SiFive RISC-V processors are pre-integrated with advanced trace, debug, and security solutions compatible with industry tools to simplify heterogeneous integration and migration. 


“RISC-V is an important element in providing additional capabilities and options for new and existing customers,” said Takeshi Kataoka, Senior Vice President, General Manager of Automotive Solution Business Unit at Renesas. “We are very excited to work with SiFive as their lead partner to develop next-generation semiconductor solutions through the collaboration of our accumulated expertise in the automotive field, and SiFive’s high-end RISC-V technologies.”

“We are excited to collaborate with Renesas to develop next-generation automotive solutions powered by the SiFive Intelligence platform,” said Patrick Little, Chairman and CEO, SiFive. “Our roadmap of advanced, high-performance RISC-V processor cores and AI accelerators will deliver significant core performance increases with the capabilities needed to meet Automotive application requirements, along with enhanced AI capabilities to power scalable, workload-accelerated solutions.”

http://www.sifive.com

Tuesday, April 13, 2021

Cerebras appoints CMO as it continues to grow

Cerebras Systems, a start-up developing a Wafer Scale Engine (WSE) chip that contains 1.2 trillion transistors, covers more than 46,225 square millimeters of silicon and contains 400,000 AI optimized compute cores, announced the appointment of Rupal Shah Hollenbeck as Vice President and Chief Marketing Officer (CMO). 

Prior to Cerebras, Hollenbeck served as senior vice president and CMO at Oracle, where she led the marketing transformation strategy for the company, while overseeing global brand and demand generation for all product areas. Previously, she held various senior leadership positions at Intel for more than two decades, most recently serving as Corporate Vice President and General Manager for Sales & Marketing in Intel’s Data Center division. Hollenbeck serves as an Independent Director of Check Point Software Technologies and is a Founding Limited Partner in Neythri Futures Fund, a venture fund dedicated to bringing diversity to the investment ecosystem.

“I am thrilled to join Cerebras’ industry-leading team as they tackle some of society’s most urgent and challenging problems with their groundbreaking CS-1 AI supercomputer,” said Hollenbeck. “I’ve been impressed with Cerebras’ customer traction over the past year, and I look forward to further accelerating this momentum with new global partnerships and customer deployments.”

Over the past year, Cerebras opened new offices in Tokyo, Japan and Toronto, Canada. The company also announced a series of wins for its flagship product, the CS-1, including deployments at Argonne National Laboratory, Lawrence Livermore National Laboratory, Pittsburgh Supercomputing Center (PSC) for its groundbreaking Neocortex AI supercomputer, EPCC, the supercomputing centre at the University of Edinburgh, and pharmaceutical leader GlaxoSmithKline.

Monday, April 12, 2021

NVIDIA outlines roadmap for BlueField data processing units (DPUs)

NVIDIA outlined a roadmap for the next two generations of its BlueField data processing unit (DPU) chips.

The current generation, BlueField-2, is now shipping and features dual 100Gb/s Ethernet or InfiniBand network ports and up to eight Arm cores. The BlueField-2 DPU includes accelerators for software-defined storage, networking, security, streaming, line rate TLS/IPSEC cryptography, precision timing for 5G telco and time-synchronized data centers and other cloud infrastructure services.

BlueField-3, which is expected to sample in the first quarter of 2022, will deliver 400GbE/NDR networking performance. It features 10x the accelerated compute power of the previous generation, with 16x Arm A78 cores and 4x the acceleration for cryptography. BlueField-3 is also the first DPU to support fifth-generation PCIe and offer time-synchronized data center acceleration. The company says BlueField-3 will enable real-time network visibility, detection and response for cyber threats and acts as the monitoring, or telemetry, agent for NVIDIA Morpheus, an AI-enabled, cloud-native cybersecurity platform, also announced today.



BlueField-3 takes advantage of NVIDIA DOCA, NVIDIA'S new data-center-on-a-chip software platform for building software-defined, hardware-accelerated networking, storage, security and management applications running on BlueField DPUs. Released today and available for download, DOCA includes a runtime environment to create, compile and optimize applications for the BlueField DPU; orchestration tools to provision, update and monitor thousands of DPUs across the data center; as well as libraries, APIs and a growing number of applications, such as deep packet inspection and load balancing.



BlueField-4 was shown on a slide with a projected 2024 horizon. It is expected to scale to 800GbE performance.

“Modern hyperscale clouds are driving a fundamental new architecture for data centers,” said Jensen Huang, founder and CEO of NVIDIA. “A new type of processor, designed to process data center infrastructure software, is needed to offload and accelerate the tremendous compute load of virtualization, networking, storage, security and other cloud-native AI services. The time for BlueField DPU has come.”

“Red Hat continues to collaborate with NVIDIA as part of an open ecosystem that accelerates innovation while providing access to the latest hardware innovations for composable infrastructure,” said Chris Wright, chief technology officer of Red Hat. “We recognize the need to develop advanced solutions for network security and automation and are excited to support BlueField DPUs and the NVIDIA Morpheus AI framework via Red Hat Enterprise Linux, Red Hat OpenShift, industry-leading containers and Kubernetes-powered hybrid cloud platform.”

“Our mutual customers are racing to harness the power of AI for enterprise applications,” said Lee Caswell, vice president of marketing for the Cloud Platform Business Unit at VMware. “The vision of enterprise infrastructure powered by the VMware Cloud Foundation and to be certified with the newly announced NVIDIA BlueField-3 DPU shows customers a path to improved application performance, a consistent operating model across virtualized and bare-metal environments, along with a new model for delivering zero-trust security without compromising performance.”

NVIDIA also disclosed that it is using its BlueField DPUs to accelerate its GeForce Now online gaming service.



NVIDIA acquires Mellanox - focus on Next Gen Data Centers

NVIDIA completed its $7 billion acquisition of Mellanox Technologies. The deal was originally announced on March 11, 2019. NVIDIA says that by combining its computing expertise with Mellanox’s high-performance networking technology, data center customers will achieve higher performance, greater utilization of computing resources and lower operating costs. “The expanding use of AI and data science is reshaping computing and data center architectures,”...


Sunday, April 11, 2021

Achronix samples 7nm Speedster FPGA

Achronix announced sampling of its 7nm Speedster 7t AC7t1500 FPGAs to customers ahead of schedule. 

The Speedster7t family targets high bandwidth workloads in AI/ML, 5G infrastructure, networking, computational storage, and test/measurement.

Achronix is leveraging TSMC's 7nm process technology.

The AC7t1500 has been optimized for high bandwidth applications and includes the industry's first 2D network-on-chip (NoC) with more than 20 Tbps of bi-directional bandwidth, 112 Gbps SerDes, PCIe Gen5, 400G Ethernet and 4 Tbps external memory bandwidth with its GDDR6 memory interfaces. The 2D NoC has dedicated high-bandwidth paths across the entire FPGA fabric interconnecting all functional blocks and peripheral I/O to each other and to the FPGA fabric. The 2D NoC eliminates complex routing bottlenecks found in traditional FPGAs and can transmit or receive 512Gbps at each of the 80 nodes across the FPGA yielding greater than 20Tbps of bidirectional bandwidth. The company says this structure simplifies routing and accelerates timing closure, allowing designers to use the available logic and memory resources to create differentiation in their designs. 

The new FPGAs also include an array of the new innovative machine learning processors (MLPs) which are ideally suited for the diverse and high-performance workloads required in AI/ML applications. The Speedster7t FPGAs are supported by the Achronix tool suite which includes Synplify Pro synthesis and the ACE place, route, and timing tools. 

https://www.achronix.com/

Engineering samples of the AC7t1500 FPGAs are shipping to customers today. Achronix expects to complete full device validation of the FPGA fabric, hard IP and peripheral interfaces in the second half of 2021 and will begin shipping production devices by the end of 2021.

  • In January 2021, Achronix entered into a definitive merger agreement with ACE Convergence Acquisition Corp. (Nasdaq: ACEV) in a transaction that would result in Achronix being listed on Nasdaq. The transaction is expected to close in the first half of 2021.

Cadence collaborates with Samsung Foundry on process nodes down to 4nm

Cadence Design Systems has optimized its chip design software for Samsung Foundry’s advanced-process technologies down to 4nm. 

The companies said Cadence digital 20.1 flow provides capabilities that are well-suited for Samsung Foundry’s advanced-process technologies. For example, the iSpatial technology allows a seamless transition from the Genus Synthesis Solution to the Innovus Implementation System using a common user interface and database. Machine learning (ML) capabilities enable users to leverage their existing designs to train the GigaOpt optimization technology to minimize design margins versus traditional place-and-route flows.

“With the ongoing innovation in hyperscale computing and autonomous driving, there is ever-increasing demand for HPC capacity,” said Sangyun Kim, vice president of the Foundry Design Technology Team, at Samsung Electronics. “By combining the latest Samsung Foundry advanced-process nodes with the Cadence 20.1 digital full flow, our customers can achieve their design goals quickly and efficiently.”

“The newly optimized Cadence digital flow makes it much simpler for customers to achieve PPA targets using Samsung Foundry’s advanced-process technologies,” said Michael Jackson, corporate vice president, R&D in the Digital & Signoff Group at Cadence. “By expanding upon our longstanding collaboration with Samsung Foundry, designers can rapidly adopt Samsung Foundry’s validated HPC methodologies to deliver exceptional silicon performance on time.”

http://www.cadence.com/go/advnodes


Tuesday, April 6, 2021

Intel intros 3rd Gen Xeon including four NFV optimized versions

Intel launched its 3rd Gen Xeon Scalable processors (code-named “Ice Lake”) featuring an average 46% improvement on popular data center workloads over the previous generation.

The new Xeon processors, which are the foundation of Intel’s data center platform, also add new and enhanced platform capabilities including Intel SGX for built-in security, and Intel Crypto Acceleration and Intel DL Boost for AI acceleration. 

The processors use Intel 10 nanometer (nm) process technology and deliver up to 40 cores per processor and up to 2.65 times higher average performance gain compared with a 5-year-old system. The platform supports up to 6 terabytes of system memory per socket, up to 8 channels of DDR4-3200 memory per socket and up to 64 lanes of PCIe Gen4 per socket.

Intel is also offering network-optimized “N-SKUs” that are designed for diverse network environments for vRAN, NFVI, virtual CDN and more.

“Our 3rd Gen Intel Xeon Scalable platform is the most flexible and performant in our history, designed to handle the diversity of workloads from the cloud to the network to the edge,” said Navin Shenoy, executive vice president and general manager of the Data Platforms Group at Intel. “Intel is uniquely positioned with the architecture, design and manufacturing to deliver the breadth of intelligent silicon and solutions our customers demand.”


https://www.intc.com/news-events/press-releases/detail/1457/intel-launches-its-most-advanced-performance-data-center

Monday, April 5, 2021

OpenFive intros Die-to-Die PHY

OpenFive, a SiFive Business Unit, introduced a Die-to-Die (D2D) PHY that complements the company’s existing D2D Controller to offer complete D2D interface solutions for various packages including substrates and interposers.

OpenFive said its new D2D PHY helps disaggregate large SoC die into smaller die, resulting in better yield, cost and power savings. It features up to 16Gbps NRZ signals with clock forwarding architecture. Each channel, comprising of 40 IOs, can provide effective throughput of up to ~1.75Tbps/mm. Users can stack up multiple channels to further increase overall throughput. The PHY also features built-in PLL, programmable output drivers, and link training state machines.

“The D2D subsystem, including both the controller and PHY, provides best-in-class latency, performance and power profile for various IO, CPU and analog chiplets,” said Ketan Mehta, Sr. Director, Product/Application Marketing, SoC IP, at OpenFive.

“OpenFive’s die-to-die connectivity IP solution will enable widespread integration of proven solutions from chiplet ecosystem partners,” said Mohit Gupta, SVP and GM SoC IP at OpenFive. “As a custom ASIC and IP provider, OpenFive is well-positioned to provide an entire chiplet solution to our customers at any stage of development, whether it be during design, integration, manufacturing, or testing of Known-Good-Die (KGD).”

http://www.openfive.com/ip

Wednesday, March 31, 2021

Arm aims v9 at secure processing from edge to core

Arm introduced its v9 architecture which is expected to become the processing basis for hundreds of billions of devices in the years ahead.

Armv9, which is the first new Arm architecture in a decade, introduces the Arm Confidential Compute Architecture (CCA)- a new method for shielding portions of code and data from access or modification while in-use, even from privileged software, by performing computation in a hardware-based secure environment.

The Arm CCA will introduce the concept of dynamically created Realms, useable by all applications, in a region that is separate from both the secure and non-secure worlds. For example, in business applications, Realms can protect commercially sensitive data and code from the rest of the system while it is in-use, at rest, and in transit. 


“As we look toward a future that will be defined by AI, we must lay a foundation of leading-edge compute that will be ready to address the unique challenges to come,” said Simon Segars, chief executive officer, Arm. “Armv9 is the answer. It will be at the forefront of the next 300 billion Arm-based chips driven by the demand for pervasive specialized, secure and powerful processing built on the economics, design freedom and accessibility of general-purpose compute.”

“Addressing the demand for more complex AI-based workloads is driving the need for more secure and specialized processing, which will be the key to unlocking new markets and opportunities,” said Richard Grisenthwaite, SVP, chief architect and fellow, Arm. “Armv9 will enable developers to build and program the trusted compute platforms of tomorrow by bridging critical gaps between hardware and software, while enabling the standardization to help our partners balance faster time-to-market and cost control alongside the ability to create their own unique solutions.”

https://www.arm.com/campaigns/arm-vision

Thursday, March 25, 2021

Analog Devices launches ASIC for O-RAN compliant radios

Analog Devices announced an ASIC-based radio platform for O-RAN compliant 5G radio units. The solution includes all the core functionality needed in an O-RAN compliant 5G radio unit, including a baseband ASIC, software-defined transceivers, signal processing, and power. 

The company says its advanced radio platform is designed to enable significant performance and form factor improvements to address the critical power consumption and cost challenges.

The Analog Devices platform allows radio designers and manufacturers to optimize total system performance for macro and small cell solutions. The reference design will enable designers to create O-RAN compliant radios with the use of:

  • ADI’s next-generation transceiver featuring advanced digital front-end signal processing (DFE), digital pre-distortion with GaN PA support, crest factor reduction, channel digital up converters and channel digital down converters.
  • A low-PHY baseband ASIC that delivers a 7.2x compliant solution for LTE, 5G and NBIoT, including IEEE1588 Precision Time Protocol and an eCPRI interface.
  • Complete clock and power chain solution

“O-RAN looks to disrupt the traditional market by rethinking the network structure with open standards that will require new and innovative radio solutions,” said Joe Barry, Vice President of Wireless Communications at Analog Devices. “ADI’s new O-RAN compliant solution marks a major step forward for the ecosystem by providing a performance optimized radio platform for 5G applications.”

“Bringing an ASIC low PHY baseband to market is a big step forward for Open RAN. Now, there is a clear path for OEMs to build competitive systems for macro and small cell,” said Andy Dunkin, Open RAN RF and Digital Platform Development Manager at Vodafone Group. “It is initiatives like this that help build a healthy ecosystem.”

http://platform.radioverse.com

http://www.analog.com/radioverse

NXP debuts Microsoft Azure Sphere-certified processor for IoT

 NXP introduced its first cloud-secured crossover applications processor, the i.MX 8ULP-CS with Azure Sphere. The processor is based on the ARM Cortex A35 is aimed at IoT applications requiring continuous security updates in the field.

Together, NXP and Microsoft are delivering a new class of secured SoCs for the IoT market. Azure Sphere provides ongoing protection, responding to emerging threats and providing continual updates to help keep devices secured. 

NXP's new i.MX 8ULP-CS processor, is cloud secured by Azure Sphere, including: the Microsoft Pluton hardware root of trust enabled on NXP EdgeLock™ secure enclave, the secured Azure Sphere OS, the cloud-based Azure Sphere Security Service and ongoing on-chip OS and security improvements from Microsoft for each device, for more than ten years. 

https://www.nxp.com/company/blog/nxp-introduces-its-first-cloud-secured-microsoft-azure-sphere-certified-processor-family:BL-I-MX-8ULP-CS

Qualcomm shows its Snapdragon 780G 5G chipset

Qualcomm Technologies introduced its Snapdragon 780G 5G Mobile Platform featuring a triple Image Signal Processor (ISP) capable of capturing from three cameras simultaneously (zoom, wide, and ultra-wide lenses).

It is powered by the 6th generation Qualcomm AI Engine with the Qualcomm Hexagon 770 processor delivering up to 12 TOPs AI performance, which is a 2x improvement compared to its predecessor. Voice and video calls can be enhanced by AI-based noise suppression and better AI-based voice assistant interactions. The platform is further enhanced by the 2nd generation Qualcomm Sensing Hub, which integrates a dedicated low-power AI processor for audio processing.

Snapdragon 780G also features an optimized Snapdragon X53 5G Modem-RF System with peak download speeds of 3.3 Gbps on sub-6 GHz frequencies. This platform takes the premium Wi-Fi 6 and Bluetooth audio features offered on Snapdragon 888 to the 7-series, for the first time, including recently debuted Qualcomm Snapdragon Sound technology. By featuring the Qualcomm® FastConnect™ 6900 Connectivity System, Snapdragon 780G supports  multi-gigabit class Wi-Fi 6 speeds (up to 3.6 Gbps), VR-class low latency and robust capacity. Further, with Wi-Fi 6E support, Snapdragon 780G is capable of extending this advanced feature set to 6 GHz spectrum as it gains momentum worldwide.

Commercial devices based on Snapdragon 780G are expected to be available in the second quarter of 2021.

https://www.qualcomm.com/products/snapdragon-780g-5g-mobile-platform


Wednesday, March 24, 2021

Samsung's 512GB DDR5 module targets bandwidth-intensive apps

Samsung Electronics began sampling a 512GB DDR5 module based on High-K Metal Gate (HKMG) process technology. 

The memory module delivers more than twice the performance of DDR4 at up to 7,200 Mbps, making it suitable for the most high-bandwidth workloads in supercomputing, artificial intelligence (AI) and machine learning (ML), as well as data analytics applications.

Samsung said its DDR5 will utilize highly advanced HKMG technology that has been traditionally used in logic semiconductors. With continued scaling down of DRAM structures, the insulation layer has thinned, leading to a higher leakage current. By replacing the insulator with HKMG material, Samsung’s DDR5 will be able to reduce the leakage and reach new heights in performance. This new memory will also use approximately 13% less power, making it especially suitable for datacenters where energy efficiency is becoming increasingly critical. The HKMG process was adopted in Samsung's GDDR6 memory in 2018 for the first time in the industry. By expanding its use in DDR5, Samsung is further solidifying its leadership in next-generation DRAM technology.

Leveraging through-silicon via (TSV) technology, Samsung’s DDR5 stacks eight layers of 16Gb DRAM chips to offer the largest capacity of 512GB. TSV was first utilized in DRAM in 2014 when Samsung introduced server modules with capacities up to 256GB.

“Samsung is the only semiconductor company with logic and memory capabilities and the expertise to incorporate HKMG cutting-edge logic technology into memory product development,” said Young-Soo Sohn, Vice President of the DRAM Memory Planning/Enabling Group at Samsung Electronics. “By bringing this type of process innovation to DRAM manufacturing, we are able to offer our customers high-performance, yet energy-efficient memory solutions to power the computers needed for medical research, financial markets, autonomous driving, smart cities and beyond.”

“As the amount of data to be moved, stored and processed increases exponentially, the transition to DDR5 comes at a critical inflection point for cloud datacenters, networks and edge deployments,” said Carolyn Duran, Vice President and GM of Memory and IO Technology at Intel. “Intel’s engineering teams closely partner with memory leaders like Samsung to deliver fast, power-efficient DDR5 memory that is performance-optimized and compatible with our upcoming Intel Xeon Scalable processors, code-named Sapphire Rapids.”


Tuesday, March 23, 2021

Intel sets course with new integrated device manufacturing strategy

Intel CEO Pat Gelsinger outlined the company’s path forward to an integrated device manufacturing model. The IDM2 strategy has 3 elements:

Building Intel’s global, internal factory network for at-scale manufacturing. Intel said its 7nm development is progressing well, driven by increased use of extreme ultraviolet lithography (EUV) in a rearchitected, simplified process flow. Intel expects to tape in the compute tile for its first 7nm client CPU  in the second quarter of this year.

Expanding the use of third-party foundry capacity to include the manufacturing for a range of modular tiles on advanced process technologies, including products at the core of Intel’s computing offerings for both client and data center segments beginning in 2023. 

Creating a new Intel Foundry Services with plans to become a major provider of U.S.– and Europe-based foundry capacity to serve the incredible global demand for semiconductor manufacturing. The new business will be headed by Dr. Randhir Thakur.  IFS will be differentiated from other foundry offerings with a combination of leading-edge process technology and packaging, committed capacity in the U.S. and Europe, and a world-class IP portfolio for customers, including x86 cores as well as ARM and RISC-V ecosystem IPs.

During the company’s global “Intel Unleashed: Engineering the Future” webcast, Intel CEO Pat Gelsinger announced a $20 billion investment to build two new fabs in Arizona, located at the company’s Ocotillo campus. 

“We are setting a course for a new era of innovation and product leadership at Intel,” said Gelsinger. “Intel is the only company with the depth and breadth of software, silicon and platforms, packaging, and process with at-scale manufacturing customers can depend on for their next-generation innovations. IDM 2.0 is an elegant strategy that only Intel can deliver – and it’s a winning formula. We will use it to design the best products and manufacture them in the best way possible for every category we compete in.” 

In addition, Intel and IBM announced plans for an important research collaboration focused on creating next–generation logic and packaging technologies.

https://newsroom.intel.com/news-releases/idm-manufacturing-innovation-product-leadership/#gs.wf9f4f

Sunday, March 21, 2021

DARPA seeks to boost domestic manufacturing of structured ASICs

The U.S. Defense Advanced Research Projects Agency (DARPA) is launching an industry collaboration with Intel to expand access to domestic manufacturing capabilities for custom chips for defense systems. 

DARPA's Structured Array Hardware for Automatically Realized Applications (SAHARA) program is partnership with Intel and academic researchers from University of Florida, University of Maryland, and Texas A&M to develop U.S.-based manufacturing capabilities to enable the automated and scalable conversion of defense-relevant field-programmable gate array (FPGAs) designs into quantifiably secure Structured ASICs. 

SAHARA will also explore novel chip protections to support the manufacturing of silicon in zero-trust environments. While FPGAs are widely used in military applications today, Structured ASICs deliver significantly higher performance and lower power consumption.

For its part, Intel said it will use its structured ASIC technology to develop platforms that significantly accelerate development time and reduce engineering cost compared to traditional ASICs. 

Intel plans to manufacture these chips using its 10nm process technology with the advanced interface bus die-to-die interconnect and embedded multi-die interconnect bridge packaging technology to integrate multiple heterogenous die in a single package.

Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs. 

"We are combining our most advanced Intel eASIC structured ASIC technology with state-of-the-art data interface chiplets and enhanced security protection, and it’s all being made within the U.S. from beginning to end. This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10nm semiconductor process," stated José Roberto Alvarez, senior director, CTO Office, Intel Programmable Solutions Group.

SAHARA is a critical program supporting the Department of Defense (DoD) microelectronics Roadmap led by the Under Secretary of Defense for Research and Engineering – USD(R&E) – to define, quantify, and standardize security while strengthening domestic semiconductor manufacturing. The Rapid Assured Microelectronics Prototypes-Commercial (RAMP-C) and State-of-the-Art Heterogeneous Integration Prototype (SHIP) projects are also integral to the DoD Roadmap.

“The structured ASIC platforms and methods developed in SAHARA together with the advanced packaging technology developed in SHIP will enable the U.S. Department of Defense to more quickly and cost effectively develop and deploy advanced microelectronic systems critical to DoD modernization priorities,” said Brett Hamilton, deputy principal director for Microelectronics in USD(R&E).

https://www.darpa.mil/news-events/2021-03-18

Lattice Semiconductor joins DARPA Toolbox Initiative

Lattice Semiconductor's Diamond and FPGA design tools for its highly reliable, low-power, small form factor FPGAs are now included in the DARPA Toolbox initiative. The DARPA Toolbox initiative is a new, agency-wide effort aimed at providing access to state-of-the-art technology from leading commercial technology vendors to the researchers behind DARPA programs.The partnership also provides DARPA organizations with access to a selection of Lattice's...

DARPA launches Data Protection in Virtual Environments

The U.S. Defense Advanced Research Projects Agency (DARPA) launched an initiative called the Data Protection in Virtual Environments (DPRIVE) program which seeks to develop a hardware accelerator for Fully Homomorphic Encryption (FHE).Fully homomorphic encryption enables users to compute on always-encrypted data, or cryptograms. The data never needs to be decrypted, reducing the potential for cyberthreats.DPRIVE aims to design and implement a hardware...

The Defense Advanced Research Projects Agency (DARPA) reached an agreement with The Linux Foundation to create open source software that accelerates United States government technology research and development innovation.Specifically, DARPA and the LF will create a broad collaboration umbrella (US Government Open Programmable Secure (US GOV OPS) that allows United States Government projects, their ecosystem, and open community to participate in accelerating...

ONF's Aether Edge Cloud selected for DARPA's Pronto Project

The Open Networking Foundation's Aether 5G Connected Edge Cloud platform is being used as the software platform for Pronto, a project backed by $30 million in DARPA funding to develop secure 5G network infrastructure. Specifically, DARPA is funding ONF to build, deploy and operate the network to support research by Cornell, Princeton and Stanford universities in the areas of network verification and closed-loop control. Aether (pronounced ‘ee-ther’)...

DARPA backs Lasers for Universal Microscale Optical Systems program

DARPA is backing a new Lasers for Universal Microscale Optical Systems (LUMOS) program, which aims to bring high-performance lasers to advanced photonics platforms. Three LUMOS Technical Areas are cited:bringing high-performance lasers and optical amplifiers into advanced domestic photonics manufacturing foundries. Tower Semiconductor and SUNY Polytechnic Institute were selected to demonstrate flexible, efficient on-chip optical gain in their...


Xilinx shrinks its UltraScale+ FPGAs with TSMC's InFO packaging

Xilinx expanded its UltraScale+ portfolio for markets with new applications that require ultra-compact and intelligent edge solutions. 

The company's Artix and Zynq UltraScale+ devices are now available in TSMC’s state-of-the-art InFO (Integrated Fan-Out) packaging technology, which is up to 70% smaller than traditional chip-scale packaging. 

“Demand for compact, intelligent edge applications is driving the requirement for processing and bandwidth engines to not only provide higher performance, but also new levels of compute density to enable the smallest form factor systems,” said Sumit Shah, senior director, Product Line Management and Marketing at Xilinx. “The new cost-optimized additions to our UltraScale+ portfolio are powerful enhancements that leverage the architecture and production-proven technology of Xilinx’s UltraScale+ FPGAs and MPSoCs, which collectively have been deployed in millions of systems worldwide.”

The Artix UltraScale+ family is built on its production-proven FPGA architecture and is designed for a range of applications including machine vision with advanced sensor technology, high-speed networking, and ultra-compact “8K-ready” video broadcasting. 

Artix UltraScale+ devices deliver 16 Gbps transceivers to support emerging and advanced protocols in networking, vision, and video, while also delivering the highest DSP compute in its class.

Fire at Renesas' Naka semiconductor fab halts production of 300mm wafers

Renesas Electronics Corporation was struck by a fire in the N3 Building (300mm line) of its Naka Factory (located in Hitachinaka, Ibaraki Prefecture) on March 19, 2021 at 2:47am.

The fire was extinguished on the same day and there no casualties to the employees and no damages to the building. However, Renesas said there was some damage to some of the utility equipment, including its pure water supply, the air conditioning system, as well as to some of the manufacturing equipment. The burned area is approximately 600m2, which is around 5% of the 12,000m2 clean room area of the first floor N3 Building, and the burned manufacturing equipment was 11 units, which is around 2% of the manufacturing equipment of the N3 Building. 


Production at N3 Building (300mm wafers) has temporarily halted while the company cleans the interior of the clean room and procures replacements of the burned equipment.

Renesas aims to resume production within one month. The financial impact from halting the N3 Building production is approximately 17 billion yen per month. 

In a press conference, company officials extended their apologies for the occurrence of the fire, the circumstances and the causes, as well as the outlook going forward. 

"We would like to give our sincerest apologies to neighboring residents, customers, partner companies, relevant authorities and all those involved for the trouble the fire caused,” said Hidetoshi Shibata, President & CEO of Renesas. “In addition, we would like to express our gratitude for the fire department and those who partook in the extinguishing of the fire.”

The production at N2 Building (200mm line) and the WT Building (wafer testing) is operating as usual. 


Thursday, March 18, 2021

Credo intros Black Hawk PAM4 retimer and gearbox DSP

Credo introduced its Black Hawk (CRT55321), a PAM4 retimer and gearbox for providing guaranteed, end-to-end signal integrity in backplane, front panel and copper applications. 

The new device, which leverages the company’s unique PAM4 DSP architecture, is a 32-lane device that supports 16 lanes on the host side and 16 lanes on the line side. The extended reach performance provides robust signal integrity for PAM4 across the most difficult channels, including legacy backplanes. The device can be used in front panel applications to drive QSFP, QSFP-DD, and OSFP optical modules, Active Electrical Cables (AEC), and passive copper cables. 

Credo said its CRT55321 Black Hawk DSP features best-in-class jitter and extended reach while operating at the lowest power consumption. The device supports built-in test and channel performance analysis capabilities such as PRBS pattern generation, internal eye monitoring and PRBS error detection. It supports IEEE standard auto-negotiation with link partners to enable more flexible applications.

“The introduction of Black Hawk DSP furthers Credo’s commitment to providing high-performance DSP for data centers, enterprise networking and high-performance computing,“ said Scott Feller, Vice President of Marketing at Credo. “Credo has leveraged its extensive analog and mixed-signal expertise to develop a unique DSP architecture to create the Black Hawk product which is 50% lower power than existing products. Credo continues to innovate with new product solutions to help solve the signal integrity issues of the next-generation data center interconnects.”

“Credo has established a significant market share in Hyperscale data centers with their retimer and gearbox solutions. The new Black Hawk device, which offers a 50% reduction in power consumption, enables those data centers to lower power consumption while driving even higher bandwidth,” says Alan Weckel, Founder and Technology Analyst at 650 Group. “As Cloud data centers deploy a larger number of 400G and 800G ports, low power solutions such as Credo’s Black Hawk will enable the migration.”

Key features

  • Support long-reach links defined in CEI-25G-LR, CEI-56G-LR-PAM4 and IEEE802.3cd
  • Support chip-to-chip and chip-to-module interfaces defined in CEI-28G-SR/VSR, CEI-56G-SR-PAM4, and IEEE 802.3bs
  • Pin-compatible with Credo’s previous generation retimer and gearbox
  • Support auto-negotiation and link training
  • Fully adaptive and programmable RX equalization with CTLE and DFE
  • Built-in diagnostics
  • IO polarity switch control

http://www.credosemi.com

Tuesday, March 16, 2021

Qualcomm completes $1.4 billion acquisition of NUVIA

Qualcomm completed its previously announced acquisition of NUVIA for $1.4 billion before working capital and other adjustments.

“The world-class NUVIA team enhances our CPU roadmap, extending Qualcomm’s leading technology position with the Windows, Android and Chrome ecosystems,” said Cristiano Amon, President and CEO-Elect, Qualcomm Incorporated. “The broad support of this acquisition from across industries validates the opportunity we have to provide differentiated products with leading CPU performance and power efficiency, as on-demand computing increases in the 5G era.”

Qualcomm Technologies expects to integrate next generation CPUs across a wide portfolio of products, including powering flagship smartphones, laptops, and digital cockpits, as well as Advanced Driver Assistance Systems, extended reality, and infrastructure networking solutions. The first Qualcomm Snapdragon platforms to feature the new internally designed CPUs are expected to sample in the second half of 2022 and will be designed for high performance ultraportable laptops.  

“We are excited to join the leading wireless innovator in the industry, driven by a common mission of inventing breakthrough technologies. Together, we will create a new class of high-performance computing platforms that set the bar for the industry,” said Gerard Williams former CEO of NUVIA, who now is SVP of Engineering at Qualcomm Technologies.

https://www.qualcomm.com/news/releases/2021/03/16/qualcomm-completes-acquisition-nuvia

  • In September 2020, NUVIA, which is headquartered in Santa Clara, California, announced a $240 million funding round led by Mithril Capital in partnership with Sehat Sutardja and Weili Dai (founders of Marvell Technology Group), funds and accounts managed by BlackRock, Fidelity Management & Research Company LLC., and Temasek, with additional participation from Atlantic Bridge, Redline Capital, Capricorn Investment Group, Dell Technologies Capital, Mayfield, Nepenthe LLC and WRVI Capital. The closure of NUVIA’s Series B round builds on a $53M Series A round, raised in November 2019. 
  •  NUVIA was founded in February 2019 by John Bruno, Manu Gulati and Gerard Williams, with the vision to create the world’s leading server processor in terms of performance per watt.

AMD sees wide partner support for new EPYC server chips

AMD unveiled its EPYC 7003 Series CPUs, claiming the highest performance benchmark for a server processor with up to 19% more instructions per clock. 

The AMD EPYC 7003 Series Processors have up to 64 “Zen 3” cores per processor and introduce new levels of per-core cache memory, while continuing to offer the PCIe 4 connectivity and class-leading memory bandwidth. 3rd Gen AMD EPYC processors also include modern security features through AMD Infinity Guard, supporting a new feature called Secure Encrypted Virtualization-Secure Nested Paging (SEV-SNP). SEV-SNP expands the existing SEV features on EPYC processors, adding strong memory integrity protection capabilities to help prevent malicious hypervisor-based attacks by creating an isolated execution environment. 

“With the launch of our 3rd Gen AMD EPYC processors, we are incredibly excited to deliver the fastest server CPU in the world. These processors extend our data center leadership and help customers solve today’s most complex IT challenges, while substantially growing our ecosystem,” said Forrest Norrod, senior vice president and general manager, Data Center and Embedded Solutions Business Group. “We not only double the performance over the competition in HPC, cloud and enterprise workloads with our newest server CPUs, but together with the AMD Instinct GPUs, we are breaking the exascale barrier in supercomputing and helping to tackle problems that have previously been beyond humanity’s reach.”

AMD also cited broad industry support, including:

  • AWS – will add the AMD EPYC 7003 series processors to its core Amazon EC2 instance families later this year.
  • Cisco – introduced new Cisco Unified Computing System (Cisco UCS) rack server models with AMD EPYC 7003 Series Processors designed to support modern hybrid cloud workloads.   
  • Dell Technologies – announced the all new PowerEdge XE8545 server with AMD EPYC 7003 series CPUs, and the company will support the new processors within its PowerEdge server portfolio.
  • Google Cloud – announced AMD EPYC 7003 series processors will power a new compute optimized VM, C2D, and an expansion of the existing general purpose N2D VM later this year. Google Cloud Confidential Computing will be available on both C2D and N2D.
  • HPE – announced it will double the lineup of AMD EPYC processor powered solutions, using the AMD EPYC 7003 series processors in new HPE ProLiant servers, HPE Apollo systems and HPE Cray EX supercomputers.
  • Lenovo – added ten Lenovo ThinkSystem Servers and ThinkAgile HCI solutions built on 3rd Gen EPYC processors, and achieved more than 25 new world records across a broad set of industry-standard benchmarks in workload areas.
  • Microsoft Azure  – announced multiple new virtual machine offerings powered by AMD EPYC 7003 series processors. Azure HBv3 virtual machines for HPC applications are generally available today, and Confidential Computing virtual machines that utilize the full security features of the new AMD EPYC 7003 series processors are in private preview.
  • Oracle Cloud Infrastructure – announced it is extending its flexible virtual machine and bare metal compute offerings with the new E4 platform based on 3rd Generation AMD EPYC Processors.
  • Supermicro – introduced the AMD EPYC 7003 series processor in its Supermicro A+ single and dual socket family of Ultra, Twin, SuperBlade, Storage and GPU Optimized Systems.
  • Tencent Cloud – announced the new Tencent Cloud SA3 server instance, powered by the 3rd Gen AMD EPYC processors.  
  • VMware – announced its latest release of VMware vSphere 7 which is optimized to take advantage of AMD EPYC processors virtualization performance, while supporting the processors’ advanced security features, including SEV-ES for both virtual machine based and containerized applications.


Monday, March 15, 2021

Lattice Semiconductor joins DARPA Toolbox Initiative

Lattice Semiconductor's Diamond and FPGA design tools for its highly reliable, low-power, small form factor FPGAs are now included in the DARPA Toolbox initiative. 

The DARPA Toolbox initiative is a new, agency-wide effort aimed at providing access to state-of-the-art technology from leading commercial technology vendors to the researchers behind DARPA programs.

The partnership also provides DARPA organizations with access to a selection of Lattice's soft IP cores and technical support to accelerate technology innovation for DARPA programs and foster the use of Lattice low-power FPGAs in DARPA-designed applications. 

“Partnering with technology innovators like Lattice through our DARPA Toolbox initiative serves to streamline access for our organizations to cutting-edge technologies,” said Serge Leef, the Microsystems Technology Office (MTO) program manager at DARPA and leader of the DARPA Toolbox initiative. “Lattice's portfolio of FPGA design tools and soft IP cores offer a compelling platform for our researchers to consider when implementing applications requiring artificial intelligence at the Edge, 5G communications, and/or automation."