Showing posts with label Silicon. Show all posts
Showing posts with label Silicon. Show all posts

Tuesday, May 10, 2022

Intel unveils IPU roadmap with ASIC and FPGA designs

Intel unveiled its IPU roadmap extending through 2026, featuring new FPGA + Intel architecture platforms (code-named Hot Springs Canyon) and the Mount Morgan (MMG) ASIC, as well as next-generation 800GB products. The discussion also a look at Intel's open-source software foundation, including the infrastructure programmer development kit (IPDK), which builds upon SPDK, DPDK and P4.

In terms of the timeline, Intel's roadmap includes:

  • 2022: Mount Evans, the company's first ASIC IPU; and Oak Springs Canyon, Intel’s second-generation FPGA IPU shipping to Google and other service providers.
  • 2023/24: introduction of 400 Gbps IPUs, code-named Mount Morgan and Hot Springs Canyon,
  • 2025/26: introduction of 800 Gbps IPUs

Here are some details on the 200 Gbps and 400 Gbps IPUs:

Mount Evans -- the code name for Intel’s first ASIC IPU, architected and developed with Google Cloud

  • Hyperscale-ready, it offers high-performance network and storage virtualization offload while maintaining a high degree of control.
  • Provides a programmable packet processing engine enabling use cases like firewalls and virtual routing.
  • Implements a hardware accelerated NVM storage interface scaled up from Intel Optane technology to emulate NVMe devices.
  • Deploys advanced crypto and compression acceleration, leveraging high- performance Intel Quick Assist technology.
  • Can be programmed using commonly deployed, existing, software environments, including DPDK, SPDK; the pipeline can be configured utilizing P4 programming.
  • Shipping is expected to begin in 2022 to Google and other service providers; broad deployment is expected in 2023.

Oak Springs Canyon -- the code name for Intel’s 2nd generation FPGA-based IPU platform built with the Intel Xeon D and the Intel Agilex FPGA, the industry’s leading FPGA in power, efficiency, and performance.

  • Network virtualization function offload for workloads like open virtual switch (OVS) and storage functions like NVMe over fabric and RoCE v2
  • Standard yet customizable platform that enables customers to customize their data path and their solutions with FPGA and Intel Xeon-D with software like Intel Open FPGA Stack, a scalable, source-accessible software and hardware infrastructure
  • Programmable using commonly deployed existing software environments, including DPDK and SPDK, which have been optimized on x86.
  • A more secure, high speed 2x 100 gigabit Ethernet network interface with the hardened crypto block
  • VirtIO support in Hardware for Native Linux support

Mount Morgan -- a next-generation ASIC IPU expected in 2023/2024.

Hot Springs Canyon -- a next-generation FPGA-based IPU platform expected in 2023/2024.

Intel demos Xeon + Tofino switch + Mount Evans IPU

As part of the Intel Innovation event this week, Intel demonstrated an Intelligent Fabric based on its Xeon Scalable processors and next-generation Xeon D processors, Tofino 3 programmable switching silicon and new "Mount Evans" infrastructure processing unit (IPU). The idea is to leverage P4 programming across all 3 processing platforms for use cases such as near real-time telemetry and analytics with the Intel Deep Insight Network Analytics...

Google collaborates on Intel's ASIC-based infrastructure processor

Intel and Google Cloud announced a deep collaboration to develop an ASIC P4-programmable infrastructure processing unit (IPU).Code-named “Mount Evans,” this open solution supports open source standards, including an infrastructure programmer development kit (IPDK) to simplify developer access to the technology in Google Cloud data centers. Machine learning, large-scale data processing and analytics, media processing, and high-performance computing...

Intel rolls FPGA-based Infrastructure Processing Unit (IPU)

Intel outlined its vision for the infrastructure processing unit (IPU), a programmable network device that intelligently manages system-level infrastructure resources by securely accelerating those functions in a data center.In a video, Guido Appenzeller, chief technology officer with Intel's Data Platforms Group says the idea is to cleanly separate the processing of client workloads from workloads of the cloud service provider.Intel cites several...

Monday, May 9, 2022

Marvell to acquire Tanzanite for Compute Express Link (CXL)

Marvell agreed to acquire privately-held Tanzanite Silicon Solutions, a start-up based in Milpitas, California that is developing advanced Compute Express Link (CXL) technologies. Terms of the all-cash transaction were not disclosed. 

Marvell said the future cloud data center will be built on fully disaggregated architecture utilizing CXL technology, requiring greater high-speed interconnectivity than ever combined with optimized compute, networking, memory, security and storage chipset solutions. Tanzanite has developed extensive expertise in CXL technology that will help further accelerate Marvell’s vision of fully composable cloud infrastructure. The benefits of CXL include infrastructure agility to instantly allocate resources tailored to workload requirements. The acquisition expands its CXL development initiatives. 

In March, Tanzanite unveiled its architectural vision and product roadmap with an SoC mapped to FPGA Proof-Of-Concept vehicle demonstrating Memory Expansion and Memory Pooling, with multi-host CXL based connectivity.

The architecture and “Smart Logic Interface Connector” SoC enables independent scaling and sharing of memory and compute in a pool with low latency within and across server racks. The Tanzanite solution provides a highly scalable architecture for exa-scale level memory capacity and compute acceleration, supporting multiple industry standard form-factors, ranging from E1.S, E3.S, memory expansion board, and memory appliance.

Tanzanite’s scalable, low latency CXL optimized fabric with caching, advanced security and RAS targets use cases:

  • Advanced Memory Expansion with optional persistency support
  • Memory Pooling and Tiering
  • CXL Switch
  • Near Memory Compute

The first generation TanzanoidTZ tiered memory appliance enables multiple CPUs to access up to 80 TB of memory capacity with 16 DDR5/32 DDR4 channel equivalent bandwidth per host, with latencies lower than dual socket servers.

“We believe that CXL will be a significant game-changer in enabling optimal resource utilization in next generation data centers, and the acquisition of Tanzanite advances our abilities to address our customers’ most challenging issues,” said Dan Christman, executive vice president, Storage Products Group, Marvell. “Marvell’s investment underscores our commitment to deliver on the promise of CXL across our industry-leading cloud portfolio spanning compute, electro-optics, networking, security and storage.”

“We are excited to see our vision for CXL leadership take a leap forward as part of Marvell, a company that is renowned for its customer-focused innovation,” said Shalesh Thusoo, CEO, Tanzanite. “CXL technologies offer a unique value proposition for a multitude of use cases and are helping shape the next generation composable data center. I’d like to thank our industry partners for their unwavering support and the entire Tanzanite team for their dedication and commitment in pioneering this technology and enabling us to achieve this milestone today.”

“The CXL standard will play a significant role in helping the industry deliver fully composable infrastructure for the cloud,” said Noam Mizrahi, corporate chief technology officer, Marvell. “The integration of CXL across our end-to-end, cloud-optimized silicon portfolio will bring new levels of data center efficiency, scalability and flexibility to power emerging metaverse and next generation AI applications.”

Marvell’s  portfolio of cloud offerings includes high-speed Alaska active electrical cable (AEC) PAM4 DSPs and Ethernet PHYs; Bravera SSD and HDD controllers; Inphi PAM4 electro-optics; COLORZ data center interconnects (DCIs); OCTEON data processor units (DPUs) for security, offload, and acceleration; Teralynx Ethernet switches; custom Arm-based server CPUs; and full custom ASICs.

Thursday, May 5, 2022

Qualcomm's Wi-Fi 7 Pro boasts 320MHz channels and >10Gbps peaks

Qualcomm Technologies has begun sampling its Wi-Fi 7 capable Qualcomm Networking Pro Series Gen 3 family of platforms featuring  intelligent multi-channel management technologies to improve speeds, lower latency, and enhance network utilization for users of Wi-Fi 6/6E devices while offering game-changing throughput and incredibly low latency for the next generation of Wi-Fi 7 client devices.

The platform is designed to  support high speed low latency wireless backhaul for home mesh Wi-Fi and enterprise infrastructure with reliable performance even in the presence of neighboring interference. 

“Qualcomm Technologies has enabled the era of 10 Gbps Wi-Fi with our first customer deliveries of the Wi-Fi 7 Networking Pro Series,” said Nick Kucharewski, senior vice president and general manager, Wireless Infrastructure and Networking, Qualcomm Technologies, Inc. “Combining support for the latest Wi-Fi 7 innovations with our unique product architecture, the platform enables solutions ranging from whole-home mesh to connectivity networks for large public venues. With this product line, we anticipate a new class of customer systems for both today’s applications and the emerging Wi-Fi 7 ecosystem.”

Highlights of the Qualcomm Networking Pro Series

  • enables systems with peak aggregate wireless capacity of 33 Gbps 
  • supports point-to-point connections exceeding 10 Gbps.
  • advanced features for interference detection and multilink operation
  • available in tri-band, and quad-band configurations for Wi-Fi connectivity across 2.4GHz, 5GHz, and 6GHz spectrum.
  • Support for Wi-Fi 7 320MHz channels (delivering a two-times increase in throughput over Wi-Fi 6) provides maximum throughput and ultra-low latency f
  • Multi-Link technology enables customer traffic to dynamically aggregate or alternate bands to avoid wireless interference and deliver deterministic, predictable low latency in heavily congested environments. 
  • When paired with leading Wi-Fi 7 client systems, like the Qualcomm FastConnect 7800, Qualcomm Networking Pro Series, Gen 3 platforms can offer support for High Band Simultaneous (HBS) Multi-Link. HBS Multi-Link leverages the high performance 5 and 6GHz bands to deliver the best throughput and latency Multi-Link performance.

The full range of platform offerings include:

  • Qualcomm Networking Pro 1620: Quad-band, 16-stream, 33.1 Gbps peak wireless capacity for stadium, large enterprise, premium home mesh systems.
  • Qualcomm Networking Pro 1220: Tri-band, 12-stream, 21.6 Gbps peak wireless capacity for enterprise, SMB, prosumer, and premium home mesh systems.
  • Qualcomm Networking Pro 820: Quad-band, 8-stream, 13.7 Gbps peak wireless capacity for enterprise, SMB, prosumer, and premium home mesh systems.
  • Qualcomm Networking Pro 620: Tri-band, 6-stream, 10.8 Gbps peak wireless capacity for enterprise, SMB, gaming, and home mesh systems.

Qualcomm debuts Wi-Fi 7

Qualcomm unveiled its FastConnect 7800 chipset offering Wi-Fi 7, Bluetooth connectivity and High Band Simultaneous Multi-link technology that leverages two Wi-Fi radios for four streams of high band connectivity in 5GHz and/or 6GHz bands. FastConnect 7800 supports all multi-link modes and with HBS Multi-Link, consumers can experience minimized latency and interference, jitter-free connections, and blazing fast speeds using 320MHz channels in increasingly...

Mediatek demos pre-standard Wi-Fi 7

MediaTek announced the world’s first live demo of pre-standard Wi-Fi 7 technology. The company is currently showcasing two Wi-Fi 7 demos to key customers and industry collaborators.Wi-Fi 7, which will utilize 2.4GHz, 5GHz and 6GHz spectrum, promises 2.4X faster speeds than Wi-Fi 6 – even with the same number of antennas – since Wi-Fi 7 can utilize 320Mhz channels and support 4K quadrature amplitude modulation (QAM) technology. Other notable features...

MaxLinear to acquire Silicon Motion for NAND flash controllers

MaxLinear agreed to acquire Silicon Motion in a cash and stock transaction that values the combined company at $8 billion in enterprise value.

Silicon Motion, which was founded in 1997 in Taipei, Taiwan, specializes in NAND flash controller integrated circuits for solid-state storage devices. The company claims that more NAND flash components, including current and up-coming generations of 3D flash produced by Intel, Kioxia, Micron, Samsung, SK Hynix, Western Digital and YMTC, are supported by Silicon Motion controllers than any other company. Silicon Motion customers include NAND flash makers, module makers, hyperscalers and OEMs.

Upon completion of the acquisition, the combined company will have a highly diversified technology platform with strong positions across the broadband, connectivity, infrastructure, and storage end markets. The combination of MaxLinear’s RF, analog/mixed-signal, and processing capabilities with Silicon Motion’s market leading NAND flash controller technology completes a total technology stack which fully captures end-to-end platform functionality and accelerates the company’s expansion into enterprise, consumer, and many other adjacent growth markets. Combined revenues are expected to be more than $2 billion annually and are supported by the technology breadth to address a total market opportunity of roughly $15 billion.

In the merger, each American Depositary Share (ADS) of Silicon Motion, which represents four ordinary shares of Silicon Motion, will receive $93.54 in cash and 0.388 shares of MaxLinear common stock, for total per ADS consideration of $114.34 (based on MaxLinear’s May 4, 2022 closing price). The strategic business combination is anticipated to drive transformational scale, create a diversified technology portfolio, significantly expand the combined company’s total addressable market, and create a highly profitable cash generating semiconductor leader.

MaxLinear intends to fund the $3.1 billion of cash consideration with cash on hand from the combined companies and fully committed debt financing from Wells Fargo Bank.

“Today’s announcement celebrates the combination of two companies that have driven significant innovation in their respective industries for over a decade,” said Kishore Seendripu, Ph.D., Chairman and CEO of MaxLinear. “The enhanced scale of the combined organization creates a new significant $2B+ player in the semiconductor industry with compelling positions across a diversified set of end-markets. MaxLinear has demonstrated a strong track record of integration success and looks for this combination to create robust growth, impressive operating margins and significant cash flows.”

“For 20 years, we have built Silicon Motion with a commitment to advancing innovation, partnering with all of our valued customers and supporting our colleagues around the world,” said Wallace Kou, President and Chief Executive Officer of Silicon Motion. “Combining Silicon Motion with MaxLinear creates significant economies of scale, accelerates our expansion into enterprise storage markets and unites unparalleled intellectual property to continue serving our customers with high-quality expertise and technical support. This transaction will deliver compelling value for shareholders, position our company to achieve our growth objectives and advance our position in high-growth storage end markets. We are very excited to partner with the MaxLinear team to take the combined company to the next level.”

Rambus to acquire Hardent for semiconductor design team

Rambus agreed to acquire Hardent, a professional services company specializing in electronic product design and engineering. The company, which is based in Montreal, has 20 years of semiconductor experience in silicon design, verification, compression, and Error Correction Code (ECC). Financial terms were not disclosed.

Rambus says the acquisition augments its team of engineers at Rambus and accelerates the development of CXL processing solutions for next-generation data centers. In addition, Hardent brings complementary IP and services to the Rambus Silicon IP portfolio, expanding the customer base and design wins in automotive and consumer electronic applications. 

“Driven by the demands of advanced workloads like AI/ML and the move to disaggregated data center architectures, industry momentum for CXL-based solutions continues to grow,” said Luc Seraphin, president and CEO of Rambus. “The addition of the highly-skilled Hardent design team brings key resources that will accelerate our roadmap and expand our reach to address customer needs for next-generation data center solutions.”

“The Rambus culture and track record of technology leadership is an ideal fit for Hardent,” said Simon Robin, president and founder of Hardent. “The team is looking forward to joining Rambus and is excited to be part of a global company advancing the future of data center solutions.”

Tuesday, April 26, 2022

SmartNIC Offload for 5G User Plane Function


Optimizing the utilization of servers is important to carriers as they look to maximize the ROI for their network infrastructure. In this video, Charlie Ashton, Senior Director of Business Development at Napatech, discusses the business benefits of offloading the 5G user plane function (UPF) to dedicated accelerators like SmartNICs and details Napatech’s UPF offload solution.

Download the 2022 SmartNICs and Infrastructure Acceleration Report:

Article: Time to start saving power, money and real estate in your 5G packet core

Solution Brief: SmartNIC offload solution for 5G User Plane Function

Ayar Labs lands $130m for In-Package Optical I/O

Ayar Labs, a start-up based in Santa Clara, California, secured $130 million in additional financing for its optical I/O solution. 

With the new investment, Ayar Labs said it is ramping production and securing supply chain partners, as signaled by previously announced multi-year strategic collaborations with Lumentum and Macom, both leaders in optical and photonic products, as well as GlobalFoundries on its new GF Fotonix platform. The company also confirmed that it made its first volume commercial shipments under contract and expects to ship thousands of units of its in-package optical interconnect by end of year.

The new funding was led by Boardman Bay Capital Management. Hewlett Packard Enterprise (HPE) and NVIDIA entered this investment round, joining existing strategic investors Applied Ventures LLC, GlobalFoundries, Intel Capital, and Lockheed Martin Ventures. Other new strategic and financial investors participating in the round include Agave SPV, Atreides Capital, Berkeley Frontier Fund, IAG Capital Partners, Infinitum Capital, Nautilus Venture Partners, and Tyche Partners. They join existing investors such as BlueSky Capital, Founders Fund, Playground Global, and TechU Venture Partners.
“As a successful technology-focused crossover fund operating for over a decade, Ayar Labs represents our largest private investment to date," said Will Graves, Chief Investment Officer at Boardman Bay Capital Management. "We believe that silicon photonics-based optical interconnects in the data center and telecommunications markets represent a massive new opportunity and that Ayar Labs is the leader in this emerging space with proven technology, a fantastic team, and the right ecosystem partners and strategy.”
“Optical connectivity will be important to scale accelerated computing clusters to meet the fast-growing demands of AI and HPC workloads,” said Bill Dally, Chief Scientist and Senior Vice President of Research at NVIDIA. “Ayar Labs has unique optical I/O technology that meets the needs of scaling next-generation silicon photonics-based architectures for AI.”
“Ayar Labs’ highly differentiated technology is crucial to supporting the high-performance computing architectures of the future,” said Paul Glaser, Vice President and Head of Hewlett Packard Pathfinder, HPE’s venture arm. “Ayar Labs represents a strategic investment opportunity for HPE to help our customers more efficiently derive greater insights and value from their data.”
“The overall financing is much larger than we originally targeted, underscoring the market opportunity for optical I/O and Ayar Labs’ leadership position in silicon photonics-based interconnect solutions,” said Charles Wuischpard, CEO of Ayar Labs. “This financing allows us to fully qualify our solution against industry standards for quality and reliability and scale production starting this year.”

What's hot at OFC22? Ayar Labs on Optical I/O

There is a lot of discussion about optical I/O and the challenge of getting photonics integrated much closer to compute units, says Mark Wade, co-founder and CTO, Ayar Labs.Last year, Ayar Labs demonstrated its end-to-end, DWDM micro-ring solution for optical I/O. This year, it's clear that big parts of the industry are heading in this direction.  Some highlights for the ecosystem include GlobalFoundries newly announced photonics platform, a...

What's hot at OFC22? GlobalFoundries on Co-packaged optics

The proof-point for co-packaged optics are here, says Anthony Yu, VP of Computing and Wired Infrastructure, GlobalFoundries. Yu discusses GlobalFoundries' newly unveiled next generation silicon photonics platform and active design wins with major customers, including collaborations with Broadcom, Cisco Systems, Marvell, NVIDIA, Ayar Labs, Lightmatter, PsiQuantum, Ranovus and Xanadu.The Consortium for Onboard Optics (COBO) has been instrumental...

Lumentum and Ayar Labs target external light sources for CPO

Lumentum and Ayar Labs announced a strategic collaboration agreement to deliver CW-WDM MSA compliant external laser sources in high volume. “Co-packaged optics to replace traditional copper interconnects is a massive new market opportunity broadly recognized by the industry and one that Lumentum is well-positioned to address with our proven laser technologies and manufacturing scale,” said Walter Jankovic, Senior Vice President and General Manager...

GlobalFoundries unveils next gen silicon photonics platform

GlobalFoundries unveiled its next generation silicon photonics platform and active design wins with major customers, including collaborations with Broadcom, Cisco Systems, Marvell, NVIDIA, Ayar Labs, Lightmatter, PsiQuantum, Ranovus and Xanadu. The platform enables a high level of integration onto a photonics integrated circuit (PIC). It also supports innovative packaging solutions, such as the passive attachment for larger fiber arrays, support...

Thursday, April 21, 2022

NTT demos first high-quality aluminum nitride transistor

 NTT demonstrated an aluminum nitride (AlN) transistor featuring a large breakdown field. The innovation is seen as a promising semiconductor material for achieving low-loss, high-voltage power devices. NTT produced the high-quality AlN by using metalorganic chemical vapor deposition (MOCVD)4 and also developed formation methods of ohmic and Schottky contacts.

NTT said that by using a wide bandgap semiconductor with a large breakdown field, it is possible to reduce the loss and increase the breakdown voltage. Therefore, wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) are being developed for power devices. UWBG semiconductors with a breakdown field larger than that of SiC or GaN further improve the performance of power devices. UWBG semiconductors include AlN, diamond, and gallium oxide (Ga2O3) (Table I). For AlN power devices, the power loss is theoretically expected to be only 5% of Si, 35% of SiC, and 50% of GaN.

In 2002, NTT succeeded in fabricating semiconducting AlN for the first time in the world, thus opening up new avenues in semiconductor device applications. Among UWBG semiconductors, AlN is advantageous in that devices can be fabricated on large-scale wafers and various device structures can be obtained by heterojunction formation with other nitride semiconductors such as GaN. However, there have been few reports on power device fabrications in this vein, and their characteristics need to be improved.

Kyocera expands manufacturing in Sendai, Japan

Kyocera unveiled plans to build the largest manufacturing facility it has ever operated in Japan, expanding production capacity for components including organic semiconductor packages and crystal device packages. 

The new facility, which will open in October 2023, will provide a 4.5-fold increase in production capacity for organic packages at the Sendai Plant Campus, as well as a substantial increase in capacity for crystal device packages.

Kyocera cites rising demand for its organic semiconductor packages and crystal device packages from 5G applications as well as automotive cameras and high-performance processors used in Advanced Driver-Assistance Systems (ADAS) and autonomous driving. 

Wednesday, April 20, 2022

MIT's novel photolithography targets thin mirrors and silicon wafers

Researchers at MIT have developed a novel photolithography technique that could significantly improve the fabrication of thin mirrors and silicon wafers.

The new approach to reshaping thin plate materials enables precise and complex shapes typically used for high-level, complex systems, like deformable mirrors or wafer-flattening processes during semiconductor manufacturing. By printing stress patterns lithographically to deform optical or semiconductor surfaces, the researchers believe future production will be more precise, scalable, and cheap.

The research is published in the April 20 issue of Optica.

Marvell adds Sara Andrews to Board

Marvell announced the appointment of Sara Andrews, Chief Information Security Officer at Experian, to its board of directors.

In addition, incumbent director Bethany Mayer, who joined the Marvell Board in 2018, has chosen to not stand for reelection at the upcoming Annual Meeting of Stockholders which is currently scheduled for June 23, 2022.

Monday, April 18, 2022

Windstream Wholesale completes 400G ZR+ trials

Windstream Wholesale completed interoperability testing of QSFP-DD form factor ZR+ pluggable modules from II-VI and Acacia, now part of Cisco. 

The tests established 400 Gigabit links in a production environment over a 1,027-kilometer link. The team also leveraged the Marvell Deneb Coherent DSP within a native 0 dBm II-VI pluggable and the Acacia module using the Greylock DSP. Industry standard oFEC algorithms were also used in the trials.

“These successful trials demonstrate that Windstream Wholesale remains the optical technology leader in making 400G wavelengths the default deployment for large wholesale and hyperscale customers,” said Buddy Bayer, president of Enterprise and Wholesale at Windstream. “Interoperability is key to simplifying high-performance networks in a cost and energy-efficient manner, and no other service provider has done more than Windstream toward making it a reality in the marketplace. This significant achievement validates Windstream’s strategy of open, disaggregated optical networking.”

Windstream also announced it has become the first service provider member of the OpenZR+ MSA. 

“We see the OpenZR+ community as well-positioned to make progress around standardization and interoperability in the high-performance transceiver arena,” said Art Nichols, vice president of network architecture and technology at Windstream. “Our goal is not simply to take advantage of our interop and optimization learnings internally, but to also contribute to the industry as a whole in driving open networking forward.”

“We would like to thank Windstream for their industry leadership in driving the technology and hosting the multivendor interoperability trials,” said Matthias Berger, vice president, coherent technology, II-VI Incorporated. “The success of these trials validates the level of maturity of the 400G ZR+ ecosystem which is essential to enable open systems and network architectures such as IP-over-DWDM.”

“As one of the founding members of the OpenZR+ MSA, we are excited to see the industry embracing interoperability and moving towards open networking architectures,” said Tom Williams, senior director of marketing for Acacia, now part of Cisco, and co-chair of the OpenZR+ MSA. “Interoperability and the introduction of new modules, such as our recently announced Bright 400ZR+ QSFP-DD pluggable, will be key to accelerating the adoption of router-based optics in transport networks.”

Karl Gass provides an overview of the OIF's 400ZR multivendor interoperability demonstration at OFC22 in San Diego, California.

Two set-ups are tested:

  • 400GE to Transport DWDM link - from an EXFO traffic generator/analyze via NeoPhotonics OSFP traversing a Cisco Open Line System to a Ciena Open Line system to a Cisco CFP-DCO in a Viavi traffic generator/analyzer
  • Round robin path consisting of 14 QSFP-DD modules, including modules from Cisco, Juniper, Ciena, Marvell, NeoPhotonics, and Fujitsu

Windstream Wholesale completes 1000 km 400G ZR+ field trials

Windstream Wholesale completed 1000 km 400G field trials leveraging pluggable modules from II-VI with QSFP-DD-DCO optics that achieve a high transmit power of 0dBm. The trials demonstrated unprecedented performance with strong working margins over a production network route and traversing up to 24 ROADMs in a lab environment.During the field trial, Windstream Wholesale closed established a 400G link on a 1,000+ kilometer link between Phoenix and...

Marvell intros low power, multi-mode 400G DSP

Marvell announced sampling of is new Deneb ultra-low power, multi-mode 400G DSP for disaggregated optical platforms. The new 7nm CDSP for 400G pluggable, which is compatible with its predecessor (Canopus), provides a seamless upgrade to interoperable pluggables across multiple platforms. Deneb can be used to enable standards based ITU, Open ROADM and OpenZR+ compliant 100G/200G/300G/400G pluggable transceivers."Standards-based interoperable...

Thursday, April 14, 2022

Renesas intros PCIe Gen6 clock buffers and multiplexers

Renesas Electronics introduced the first clock buffers and multiplexers that meet stringent PCIe Gen6 specifications. 

Renesasis offering 11 new clock buffers and 4 new multiplexers. The new devices, which also support and provide extra margin for PCIe Gen5 implementations, complement Renesas’ low-jitter 9SQ440, 9FGV1002 and 9FGV1006 clock generators to offer customers a complete PCIe Gen6 timing solution for data center/cloud computing, networking and high-speed industrial applications.

The PCIe Gen6 standard supports extremely high data rates of 64 GT/s while requiring very low clock jitter performance of less than 100fs RMS. Renesas’ new RC190xx clock buffers and RC192xx multiplexers have PCIe Gen6 additive jitter specs of only 4fs RMS, making them virtually noiseless, and thereby future-proofing customer designs for the next generation of industry standards.

“PCIe Gen6 timing will be at the heart of new equipment in data centers, high-speed networking and other applications,” said Zaher Baidas, Vice President of the Timing Products Division at Renesas. “As we have done for preceding generations, Renesas is providing customers with the first timing solution to enable these new, higher-performance systems. Our customers know that we have the technical expertise and market knowledge to ensure that their products will be able to meet future requirements as well.”

Wednesday, April 13, 2022

Marvell has shipped more than 3 million 400G switch ports to date

Marvell has more than doubled its growth year-over-year (YOY) in cloud data center Ethernet switch port shipments, based on 650 Group's quarterly switch report for Q4'21 released last month. 

The company said its share of the overall data center switch market grew from 6% to 10% YOY and specifically within the 50G SerDes segment of switches, deployed by the fast-growing cloud infrastructure market, the company attained a record high of 31% share in Q4'21. 

Notably, Marvell confirmed that it has shipped more than 3 million 400G switch ports to date.

"The continued, and growing, traction of Marvell's Teralynx switch family in tier-1 cloud data centers demonstrates its compelling value proposition for customers requiring the best possible application performance," said Guy Azrad, senior vice president and general manager, Switch Business Unit at Marvell. "Our Teralynx switches are built upon a highly efficient and scalable architecture which delivers the power efficiency and roadmap for 51.2 Tbps and beyond. Further, the Teralynx family is uniquely positioned for integration with Marvell's high-speed electro-optics offerings to bring a complete and better-together, end-to-end cloud solution."

"The Ethernet switch market reached a new all-time high in 4Q'21, exceeding a $9 billion per quarter run-rate for the first time, driven by cloud data centers," said Alan Weckel, founding analyst for 650 Group. "This past quarter, our research found that Marvell's market share reached 31% for 50G SerDes shipments, achieving the highest to date, with growth YoY at 104%."

"Our leading cloud data center customers have been ramping their volume deployments with Marvell's Teralynx switches and our optical modules to optimize their infrastructure," said Osa Mok, chief marketing officer at Innolight Technology. "Marvell brings a comprehensive switch and PAM4 electro-optics platform solution that complements our module capabilities to help our customers meet the bandwidth-intensive requirements of 400G connectivity."

"The surge in cloud infrastructure build-out is driving the demand for low-latency and high-performance networking solutions that can meet the exacting requirements for 400G and beyond connectivity," said Supriyo Dey, VP of Business Development at Eoptolink. "Marvell's cloud-optimized Teralynx switches along with our optical transceivers are addressing the increasing ramp from cloud data customers as they scale to volume deployments."

Marvell to acquire Innovium for data center switching silicon

Marvell Technology agreed to acquire Innovium, a start-up offering switching silicon for cloud and edge data centers, in an all-stock transaction valued at $1.1 billion.Innovium, which is based in San Jose, California, offers high-performance switching silicon solutions for cloud and edge data centers. The company was founded in 2014 and has approximately 230 employees.Marvell, which has an extensive portfolio of Ethernet switch semiconductor solutions,...

Innovium shipped over one million 400G ports in 2020

Innovium, a start-up offering high-performance switching silicon, shipped over one million 400G TERALYNX switch silicon ports in 2020. The company said it is seeing a rapid ramp of 400G connectivity by top cloud customers using its TERALYNX based switches. “2020 was a great year for Innovium. Demand for bandwidth accelerated across all cloud data centers driven by worldwide growth in online businesses, remote everything and digitization...

Interface Masters develops switch with Intel Tofino 2 + AMD EPYC 2

Interface Masters Technologies introduced a network switch based on the Intel Tofino 2 P4-programmable switch fabric (12.8Tb) and a Dual AMD EPYC 2 Milan 64-core offload processors.

“Interface Masters is an OEM hardware solutions provider. Our new Tahoe 2664-ZR1 is entirely designed and manufactured in the USA – our hardware is never compromised and always secure,” says Interface Masters VP Product, Brian Shannon. “AMD’s EPYC 2 Milan CPU is a powerhouse and the Intel Tofino 2 switch supports an incredible out-of-the-box software suite. The switch is manufactured, tested and shipped from San Jose, California – and ready for our customer’s software load.”

Software configurations include white box with ONIE SDK and a complete hardware specific SDK tool set for custom development. Intel Deep Insight, Intel P4 Studio SDE, development tools and software partner solutions are available. Interface Masters also currently offers SONiC, DENT and Stratum support for Intel Tofino 2.

Intel to acquire Barefoot Networks for programmable switch silicon

Intel agreed to acquire Barefoot Networks, a start-up developing programmable Ethernet switch silicon and software for use in the data center. Financial terms were not disclosed. Intel said the acquisition will support its focus on end-to-end cloud networking and infrastructure, enabling it to better compete in the Ethernet switching segment. Barefoot, which is based in San Jose, California, is shipping the second generation of its P4-programmable...

Barefoot's Tofino 2 chip delivers 12.8 Tbps switching for 32x400GE

Barefoot Networks is now sampling its Tofino 2 chip, the second generation of its P4-programmable Tofino Ethernet switch application-specific integrated circuit (ASIC) family. Tofino 2 doubles the performance of the first generation Tofino chip, now delivering 12.8 Tbps of packet processing capacity for hyperscale data centers, cloud, enterprise and service provider networks. The device leverages 7nm process technology and is designed for full P4-programmability. Tofino...