Showing posts with label Silicon. Show all posts
Showing posts with label Silicon. Show all posts

Tuesday, September 22, 2020

Arm expands its Neoverse data center server CPU porfolio

Arm is unveiling two new platforms in its Neoverse silicon portfolio for data centers CPUs: 

  • the Arm Neoverse V1 platform, delivering a single-threaded performance uplift of more than 50% over N1 and aimed at applications more reliant on CPU performance and bandwidth. Neoverse V1 supports Scalable Vector Extensions (SVE), which enables execution of single-instruction multiple dispatch (SIMD) integer, bfloat16, or floating-point instructions on wider vector units using a software programming model that’s agnostic to the width of the unit. Arm says SVE will ensure portability and longevity of the software code, along with efficient execution. Potential markets include high-performance cloud, HPC, and machine learning.
  • the Neoverse N2, which is the second-generation N-series platform, and aimed at the scale-out performance needs of applications across a range of use cases, from cloud to SmartNICs and enterprise networking, to power-constrained edge devices.  Neoverse N2 offers 40% higher single-threaded performance, compared to Neoverse N1, and retains the same level of power and area efficiency as Neoverse N1.
Arm's Neoverse roadmap now extends from 7nm devices currently in production, to 5nm designs in 2021 and 3nm in 2022.


Arm cited growing momentum for its Neoverse silicon across a range of data center applications. Operating systems and hypervisors, Xen, KVM, Docker containers, and, increasingly, Kubernetes have all announced support for Arm. 

http://www.arm.com



Thursday, August 20, 2020

DARPA’s Electronics Resurgence Initiative signs Arm

Arm today announced a three-year partnership agreement with the U.S. Defense Advanced Research Projects Agency (DARPA), establishing an access framework to all commercially available Arm technology.

Under DARPA’s Electronics Resurgence Initiative, the research community that supports DARPA’s programs will gain access to Arm’s IP, tools and support programs.

“The span of DARPA research activity opens up a huge range of opportunities for future technological innovation,” said Rene Haas, president, IP Products Group, Arm. “Our expanded DARPA partnership will provide them with access to the broadest range of Arm technology to develop compute solutions supported by the world’s largest ecosystem of tools, services and software.”

“DARPA’s programs within the Microsystems Technology Office (MTO) focus on the most advanced challenges in microelectronics; equipping our community with best in class technologies is essential not only for break-through scientific and engineering advances, but also for improved transition into military and commercial applications,” stated Serge Leef, who leads design automation and secure hardware programs in MTO.

https://www.darpa.mil/work-with-us/electronics-resurgence-initiative

Tuesday, August 18, 2020

Fungible announces its DPU for scale-out data centers

Fungible, a start-up based in San Jose, California, unveiled its Fungible Data Processing Unit (Fungible DPU), a microprocessor optimized for data interchange and data-centric computation in scale-out architectures.

Fungible describes its DPU as the "third socket" in data centers, complementing the CPU and GPU, and delivering significant gains in performance, footprint and cost efficiencies for next-generation, scale-out networking, storage, security, and analytics platforms.  The company cites two core innovations that are tightly interwoven:

  • A programmable data-path engine that executes data-centric computations at extremely high speeds, while providing flexibility comparable to general-purpose CPUs. The engine is programmed in C using industry-standard toolchains and is designed to execute many data-path computations concurrently. 
  • A new network engine that implements the endpoint of a high-performance TrueFabric that provides deterministic low latency, full cross-section bandwidth, congestion and error control, and high security at any scale (from 100s to 100,000s of nodes). The TrueFabric protocol is fully standards-compliant and interoperable with TCP/IP over Ethernet, ensuring that the data center leaf-spine network can be built with standard Ethernet switches and standard electro-optics and fiber infrastructure.

Fungible is launching two versions of its DPU:
  • Fungible F1 DPU – an 800Gbps processor designed specifically for high performance storage, analytics and security platforms.
  • Fungible S1 DPU – a 200Gbps processor optimized for host-side use cases including bare metal virtualization, storage initiator, NFVi/VNF applications and distributed node security.
Fungible also provides a full suite of software that enables the Fungible DPU and the products it powers to be used "out of the box". This includes data-path stacks, host drivers and agents for x86, and a set of centralized cluster services that provides management, control and visibility of a large number of Fungible DPU-enabled products.

"The Fungible DPU is purpose built to address two of the biggest challenges in scale-out data centers – inefficient data interchange between nodes and inefficient execution of data-centric computations," said Pradeep Sindhu, CEO and Co-Founder of Fungible. "Data-centric computations are increasingly prevalent in data centers, with important examples being the computations performed in the network, storage, security and virtualization data-paths. Today, these computations are performed inefficiently by existing processor architectures. These inefficiencies cause overprovisioning and underutilization of resources, resulting in data centers that are significantly more expensive to build and operate. Eliminating these inefficiencies will also accelerate the proliferation of modern applications, such as AI and analytics."

https://www.fungible.com/


Fungible raises $200 million for Data Processing Units (DPUs)

Fungible, a start-up based in Santa Clara, California, closed $200 million in Series C financing for its efforts to create an entirely new category of programmable processor.

The Fungible Data Processing Unit (DPU) aims to deliver an order of magnitude improvement in the execution of data-centric workloads. The company sees its DPU as a fundamental building block for next-generation data centers.

Fungible has not yet announced its first products. In previous blog posts, Fungible has talked about Composable Disaggregated Infrastructure (DCI), where compute and storage resources are stored in separate servers and interconnected by a very high bandwidth, reliable and low-latency IP over Ethernet (IPoE) network fabric.

Fungible was founded by Pradeep Sindhu and Bertrand Serlet. Sindhu previously founded Juniper Networks, held roles as CEO and CTO, and is now chief scientist. Serlet previously founded a storage startup and before that was senior vice president of software engineering at Apple.

The latest funding was led by the SoftBank Vision Fund with participation from Norwest Venture Partners and existing investors, including Battery Ventures, Mayfield Fund, Redline Capital and Walden Riverwood Ventures. Fungible has raised $300 million to date.

SiFive and Innovium enter collaboration

SiFive and Innovium, announced a collaboration to drive faster innovation in switch silicon solutions.

SiFive specializes in RISC-V processor IP and silicon solutions. Innovium is known for its networking switch silicon for cloud and edge data centers.

The companies are collaborating on new designs that incorporate SiFive E2-Series processor cores to extend Innovium’s programmable switch silicon.

Innovium’s TERALYNX offers customers a highly differentiated and comprehensive programmable switch silicon portfolio, from 1 to 25.6Tbps performance and an architecture scaling to 51.2Tbps+, with consistent features and software.

“As Innovium’s highly successful TERALYNX switches ramp in Cloud and Edge data centers, we continue to invest in an industry-leading roadmap for next-generation networks,” said Rajiv Khemani, CEO of Innovium, Inc. “We are pleased to use SiFive’s processor IP in our products for additional flexible and programmable capabilities in the areas of management and configuration.”

“SiFive’s winning processor portfolio is well suited to new designs for datacenter infrastructure thanks to the highly-efficient, silicon-proven, configurable cores we offer,” said Dr. Naveed Sherwani, Chairman, President & CEO of SiFive. “The data center market is searching for efficient and scalable networking solutions that, through collaborating with Innovium, we can help provide.”

SiFive raises $61 million for RISC-V

SiFive, a start-up specializing in RISC-V processor IP and silicon solutions,  raised $61 million in a Series E round.

SiFive, which is based in San Mateo, California, develops a range of processor cores, accelerators, and SoC IP to create domain-specific architecture that will enable efficient, high-performance computing solutions. Recently, SiFive announced the SiFive 20G1 update for SiFive Core IP, enabling significant enhancements for performance, power, area, and features, with pre-integrated SiFive Shield, for whole SoC security, and SiFive Insight advanced trace and debug capabilities.

The latest funding round was led by SK hynix, joined by new investor Prosperity7 Ventures, with additional funding from existing investors, Sutter Hill Ventures, Western Digital Capital, Qualcomm Ventures LLC, Intel Capital, Osage University Partners, and Spark Capital.

Innovium raises $170 million for its switching silicon

Innovium, a start-up based in San Jose, California, raised $170 million for its switching silicon solutions cloud and edge data centers.

The new funding round included investments from Premji Invest, DFJ Growth, funds and accounts managed by BlackRock, and multiple strategic investors, along with existing investors including Greylock, Capricorn, WRVI, Qualcomm Ventures, Redline, S-Cubed Capital and DAG

. Innovium said this latest funding makes it the first network silicon company to achieve billion-dollar valuation "unicorn" status.

Earlier this year, Innovium unveiled its TERALYNX 8 silicon boasting 25.6Tbps switch with 112G SerDes

In addition, Innovium noted the following milestones during 1H 2020:

  • Continued volume production ramp of TERALYNX 7
  • Ramping TERALYNX 5 shipments for ToR, Edge & 5G customer designs
  • Revenue growth of over 5x in 1H 2020 vs 1H 2019
  • Achieved over 20% market share in 50G WW SerDes shipments and emerged as the only credible silicon diversity option [1]
  • Wins, deployments and trials at majority of top 25 Cloud customers in the world

“We are delighted at the strong adoption at leading OEM, Cloud and ODM customers for our TERALYNX® family, which resulted in over 20% market share for 50G SerDes switch silicon in our first year of shipments. This additional funding, achieved despite ongoing macroeconomic uncertainty, validates our vision, execution and momentum in a multi-billion secular high-growth market,” said Rajiv Khemani, Co-founder and CEO of Innovium.

“Data centers are expected to see secular long-term expansion from Cloud, 5G, AI and remote-work applications. Innovative TERALYNX switch silicon products from Innovium have already been adopted by world’s leading hyperscale Cloud providers and leading OEMs including Cisco. We are excited to partner with Innovium for its roadmap innovation and help accelerate go-to-market ramp up,” said TK Kurien, Managing Partner and Chief Investment Officer at Premji Invest.

https://www.innovium.com/

Innovium pushes switching silicon to 25.6 Tbps with support for 112G PAM4

Innovium unveiled its TERALYNX 8 networking switch silicon featuring a massive 25.6 Tbps capacity and support for 112G PAM4 SerDes I/O. This next-generation TERALYNX 8 design features deep programmability, the largest on-chip buffers, and advanced telemetry capabilities.

Innovium's TERALYNX 8 switch, which is aimed at hyperscale data centers and which is expected to sample in the second half of 2020, could be used for highly compact, highest port-density single-chip switches for 100G to 800G configurations, including 1RU, 32 x 800G switch. The silicon will be delivered in a single 7nm die fabricated by TSMC.

Innovium confirmed that its current generation, 12.7 Tbps switching silicon is already being used by numerous commercial customers, including some of the biggest cloud provider networks.

MediaTek intros 5G chip supporting dual SIM

MediaTek introduced its Dimensity 800U 5G SoC, designed for multi-core high performance and leading 5G+5G Dual Sim Dual Standby (DSDS) technology.

The 7nm SoC has an octa-core CPU with a dual cluster consisting of two Arm Cortex-A76 processors with a clock speed of 2.4GHz and six Arm Cortex-A55 processors with a clock speed of 2.0GHZ. Dimensity 800U integrates an Arm Mali-G57 GPU, an independent AI processing unit (APU) and LPDDR4x RAM.

In addition, the integrated 5G modem in MediaTek's Dimensity 800U not only supports sub-6Ghz SA and NSA networks, but also supports 5G+5G dual SIM dual standby (DSDS), dual Voice over New Radio (VoNR), and 5G two carrier aggregation (2CC 5G-CA).

"MediaTek has always focused on enhancing the user experience with our leading semiconductor technology, whether consumers are streaming, gaming or taking photos," said Dr. Yenchi Lee, Deputy General Manager of MediaTek's Wireless Communications Business Unit. "MediaTek's Dimensity 800U brings cutting-edge, next-gen technology to the Dimensity SoC series, bringing MediaTek's advanced 5G, imaging and multimedia technologies to high-performance 5G smartphones that deliver incredible 5G experiences."

Key features

  • Support for 120Hz FHD+ displays with high refresh rates for faster and smoother gaming and media streaming.
  • Support for the HDR10+ standard for enhanced visual quality, plus the integrated MediaTek MiraVision PQ engine with HDR optimization for various types of videos.
  • Support for flexible camera placement with up to 64MP cameras and quad camera capabilities.
  • Integrated APU and ISP to provide a series of AI camera-enhancing functions.
  • Support for voice on wakeup (VoW) and dual-mic noise reduction technology, lowering the standby power consumption of a voice assistant, and enabling it to hear clear sound regardless of external noise interruptions.


Monday, August 17, 2020

Lightmatter is developing a photonic processor

Lightmatter, a start-up based in Boston, will unveil plans for an artificial intelligence (AI) photonic processor.

Lightmatter said its general-purpose AI inference accelerator will use light to compute and transport data. The 3D-stacked chip package contains over a billion FinFET transistors, tens of thousands of photonic arithmetic units, and hundreds of record-setting data converters. Lightmatter’s photonic processor runs standard machine learning frameworks including PyTorch and TensorFlow, enabling state-of-the-art AI algorithms.

“The Department of Energy estimates that by 2030, computing and communications technology will consume more than 8 percent of the world’s power. Transistors, the workhorse of traditional processors, aren’t improving; they’re simply too hot. Building larger and larger datacenters is a dead end path along the road of computational progress,” said Nicholas Harris, PhD, founder and CEO at Lightmatter. “We need a new computing paradigm. Lightmatter’s optical processors are dramatically faster and more energy efficient than traditional processors. We’re simultaneously enabling the growth of computing and reducing its impact on our planet.”

On August 18th, Lightmatter’s VP of Engineering, Carl Ramey, will present their photonic processor architecture at HotChips32.

https://lightmatter.co/

Wednesday, August 12, 2020

Samsung implements "X-Cube" 3D IC packaging in 7nm and 5nm

Samsung Electronics announced the immediate availability of its 3D IC packaging technology, eXtended-Cube (X-Cube).

"Samsung's new 3D integration technology ensures reliable through-silicon via (TSV) interconnections even at the cutting-edge EUV process nodes," said Moonsoo Kang, senior vice president of Foundry Market Strategy at Samsung Electronics. "We are committed to bringing more 3D IC innovation that can push the boundaries of semiconductors.”

The X-Cube test chip built on 7nm uses TSV technology to stack SRAM on top of a logic die, freeing up space to pack more memory into a smaller footprint. Enabled by 3D integration, the ultra-thin package design features significantly shorter signal paths between the dies for maximized data transfer speed and energy efficiency. Customers can also scale the memory bandwidth and density to their desired specifications.

Samsung X-Cube's silicon-proven design methodology and flow are available now for advanced nodes including 7nm and 5nm. Building on the initial design, Samsung plans to continue collaborating with global fabless customers to facilitate the deployment of 3D IC solutions in next-generation high-performance applications.

Tuesday, August 11, 2020

SiFive raises $61 million for RISC-V

SiFive, a start-up specializing in RISC-V processor IP and silicon solutions,  raised $61 million in a Series E round.

SiFive, which is based in San Mateo, California, develops a range of processor cores, accelerators, and SoC IP to create domain-specific architecture that will enable efficient, high-performance computing solutions. Recently, SiFive announced the SiFive 20G1 update for SiFive Core IP, enabling significant enhancements for performance, power, area, and features, with pre-integrated SiFive Shield, for whole SoC security, and SiFive Insight advanced trace and debug capabilities.

The latest funding round was led by SK hynix, joined by new investor Prosperity7 Ventures, with additional funding from existing investors, Sutter Hill Ventures, Western Digital Capital, Qualcomm Ventures LLC, Intel Capital, Osage University Partners, and Spark Capital.

“Global demand for storage and memory in the data center is increasing as AI-powered business intelligence and data processing growth continues”, said Youjong Kang, VP of Growth Strategy, SK hynix. “SiFive is well-positioned to grow with opportunities created from data center, enterprise, storage and networking requirements for workload-focused processor IP.”

http://www.sifive.com

Monday, July 27, 2020

Intel names a new tech team in wake of 7nm delays

Intel announced major leadership changes to its technology team, including the departure of Murthy Renduchintala, the company's Chief Engineering Officer. The news follows last week's disclosure that Intel's introduction of 7nm technology will be delayed by six months to a year.

Intel CEO Bob Swan said the changes are intended to accelerate product leadership and improve focus and accountability in process technology execution.

Intel's Technology, Systems Architecture and Client Group (TSCG) will be separated into the following teams:

  • Technology Development, led by Dr. Ann Kelleher. An accomplished Intel leader, Kelleher has been head of Intel manufacturing, where she ensured continuous operations through the COVID-19 pandemic while increasing supply capacity to meet customer needs and accelerating the ramp of Intel’s 10nm process. She will now lead Intel technology development focusing on 7nm and 5nm processes. Dr. Mike Mayberry, who has been leading Technology Development, will consult and assist in the transition until his planned retirement at the end of the year. Mayberry has a 36-year track record of innovation at Intel, during which he has made key contributions in technology development and as the leader of Intel Labs.
  • Manufacturing and Operations, led by Keyvan Esfarjani. Esfarjani most recently led manufacturing for Intel’s Non-Volatile Memory Solutions Group (NSG), in which role he set the vision and strategy for Intel’s memory manufacturing and led a rapid expansion of capacity. He will now lead global manufacturing operations and continue Kelleher’s work driving product ramp and the build-out of new fab capacity.
  • Design Engineering, led in the interim by Josh Walden while Intel conducts an accelerated global search to identify a permanent world-class leader. Walden is a proven leader in technology manufacturing and platform engineering. Most recently, he has been leading the Intel Product Assurance and Security Group (IPAS), which will continue to report to him.
  • Architecture, Software and Graphics will continue to be led by Raja Koduri. Koduri has responsibility for driving the development of Intel’s architecture and software strategy, and dedicated graphics product portfolio. Under his leadership, we will continue to invest in our software capability as a strategic asset and further build-out software engineering with cloud, platform, solutions and services expertise.
  • Supply Chain will continue to be led by Dr. Randhir Thakur.  Thakur will report directly to the CEO as chief supply chain officer, recognizing the ever-growing importance of this role and our relationships with key players in the ecosystem. Thakur and his team are charged with ensuring supply chain is a competitive advantage for Intel.

“I look forward to working directly with these talented and experienced technology leaders, each of whom is committed to driving Intel forward during this period of critical execution,” said Swan. “I also want to thank Murthy for his leadership in helping Intel transform our technology platform. We have the most diverse portfolio of leadership products in our history and, as a result of our six pillars of innovation and disaggregation strategy, much more flexibility in how we build, package and deliver those products for our customers.”

Thursday, July 23, 2020

Marvell intros a customizable ASIC in 5nm

Marvell debuted a cutomizable ASIC that to deliver processing power for applications ranging from next generation 5G carriers, cloud data centers, enterprise and automotive.

Marvell’s new ASIC solution enables a multitude of customization options and a differentiated approach with best-in-class standard product IP including Arm-based processors, embedded memories, high-speed SerDes, networking, security and a wide range of storage controller and accelerators in 5nm and below.

With its legacy as part of IBM, GlobalFoundries and AveraSemi, the Marvell ASIC team brings decades of expertise with the custom ASIC model across 14 leading-process nodes and has produced over 2,000 custom ASICs.

“The future of compute requires scalable and highly optimized solutions that can power the data center all the way to the network edge,” said Mohamed Awad, vice president of Marketing, Infrastructure Line of Business, Arm. “Marvell brings a fresh and differentiated approach to addressing these requirements by uniquely utilizing Arm platforms to improve power, performance, and time-to-market for our mutual partners.”

“Marvell custom ASIC has a rich history in significant customization, advanced interfaces and memory solutions. Our ability to pull optimized components, like the Arm processor subsystem, from across Marvell’s product portfolio adds a whole new dimension to what we can deliver,” said Kevin O’Buckley, general manager of the ASIC BU at Marvell. “The breadth of Marvell’s infrastructure technology portfolio is unique in the industry – and is available in one comprehensive offering. We see this as an opportunity to deliver greater value to our existing customers while opening up possibilities for custom silicon implementations that had not previously been viable.”

Key features of Marvell’s 5nm and beyond ASIC:

  • Leading Arm-based processor technologies
  • Pre-optimized processor IP to improve power, performance, and time-to-market
  • Multiple power-optimized SerDes solutions at 112G and beyond
  • Ability to solve demanding system topologies at reduced system cost
  • Advanced packaging solutions for chiplets, integrated memory and optics
  • Lower board and ASIC costs
  • Simpler system integration
  • Bandwidth scaling and power reduction enabled with world-class SerDes
  • Enhanced security, networking and memory IP for the most demanding applications


https://www.marvell.com/products/custom-asic.html

Tuesday, July 21, 2020

Innovium raises $170 million for its switching silicon

Innovium, a start-up based in San Jose, California, raised $170 million for its switching silicon solutions cloud and edge data centers.

The new funding round included investments from Premji Invest, DFJ Growth, funds and accounts managed by BlackRock, and multiple strategic investors, along with existing investors including Greylock, Capricorn, WRVI, Qualcomm Ventures, Redline, S-Cubed Capital and DAG

. Innovium said this latest funding makes it the first network silicon company to achieve billion-dollar valuation "unicorn" status.

Earlier this year, Innovium unveiled its TERALYNX 8 silicon boasting 25.6Tbps switch with 112G SerDes

In addition, Innovium noted the following milestones during 1H 2020:

  • Continued volume production ramp of TERALYNX 7
  • Ramping TERALYNX 5 shipments for ToR, Edge & 5G customer designs
  • Revenue growth of over 5x in 1H 2020 vs 1H 2019
  • Achieved over 20% market share in 50G WW SerDes shipments and emerged as the only credible silicon diversity option [1]
  • Wins, deployments and trials at majority of top 25 Cloud customers in the world

“We are delighted at the strong adoption at leading OEM, Cloud and ODM customers for our TERALYNX® family, which resulted in over 20% market share for 50G SerDes switch silicon in our first year of shipments. This additional funding, achieved despite ongoing macroeconomic uncertainty, validates our vision, execution and momentum in a multi-billion secular high-growth market,” said Rajiv Khemani, Co-founder and CEO of Innovium.

“Data centers are expected to see secular long-term expansion from Cloud, 5G, AI and remote-work applications. Innovative TERALYNX switch silicon products from Innovium have already been adopted by world’s leading hyperscale Cloud providers and leading OEMs including Cisco. We are excited to partner with Innovium for its roadmap innovation and help accelerate go-to-market ramp up,” said TK Kurien, Managing Partner and Chief Investment Officer at Premji Invest.

https://www.innovium.com/

Innovium pushes switching silicon to 25.6 Tbps with support for 112G PAM4

Innovium unveiled its TERALYNX 8 networking switch silicon featuring a massive 25.6 Tbps capacity and support for 112G PAM4 SerDes I/O. This next-generation TERALYNX 8 design features deep programmability, the largest on-chip buffers, and advanced telemetry capabilities.

Innovium's TERALYNX 8 switch, which is aimed at hyperscale data centers and which is expected to sample in the second half of 2020, could be used for highly compact, highest port-density single-chip switches for 100G to 800G configurations, including 1RU, 32 x 800G switch. The silicon will be delivered in a single 7nm die fabricated by TSMC.

Innovium confirmed that its current generation, 12.7 Tbps switching silicon is already being used by numerous commercial customers, including some of the biggest cloud provider networks.

Some TERALYNX 8 highlights

  • 112G SerDes IO with best economics for next-generation switches
  • Up to 256 long-reach (LR) 112G PAM4 SerDes to enable switch configurations such as 32 x 800G, 64 x 400G, 128 x 200 and 256 x 100G
  • Enables industry’s most compact 32 x 800G (25.6 Tbps) switch in 1RU form factor
  • Enables a range of connectivity options, including 10/25/50/100/200/400 GbE
  • Range of pin-compatible SKU options, including 25.6 Tbps, 12.8 Tbps and 8Tbps
  • Largest on-chip buffer of 170 MB for a data-center switch
  • Highest radix with 256 ports to help flatten network tiers
  • INNOFLEX programmable forwarding pipeline offers unmatched flexibility and feature-set
  • Enhanced forwarding and ACL table scales
  • Robust RoCE, PFC and rich QoS necessary for distributed storage, HPC and AI applications
  • FLASHLIGHT™ v3 telemetry and analytics solves toughest troubleshooting problems
  • Hardware driven in-band and streaming telemetry available at line-rate
  • Additional innovations for deep analytics correlated to applications
  • Unique predictive and actionable information versus reactive data overload seen in alternative switch providers
  • Industry’s most scalable and fully compatible product line from 1 to 25.6T
  • Full SW and architecture compatibility with TERALYNX 5 & TERALYNX 7

Monday, July 13, 2020

Analog Devices to buy Maxim Integrated Products

Analog Devices agreed to acquire Maxim Integrated Products in an all stock transaction that values the combined enterprise at over $68 billion.

Maxim stockholders will receive 0.630 of a share of ADI common stock for each share of Maxim common stock. Upon closing, current ADI stockholders will own approximately 69 percent of the combined company, while Maxim stockholders will own approximately 31 percent.

ADI said the combination strengthens its analog semiconductor leadership position with expected revenue of $8.2 billion and free cash flow of $2.7 billion1 on a pro forma basis. Maxim’s strength in the automotive and data center markets, combined with ADI’s strength across the broad industrial, communications and digital healthcare markets are highly complementary and aligned with key secular growth trends. With respect to power management, Maxim’s applications-focused product offerings complement ADI’s catalog of broad market products.

“Today’s exciting announcement with Maxim is the next step in ADI’s vision to bridge the physical and digital worlds. ADI and Maxim share a passion for solving our customers’ most complex problems, and with the increased breadth and depth of our combined technology and talent, we will be able to develop more complete, cutting-edge solutions,” said Vincent Roche, President and CEO of ADI. “Maxim is a respected signal processing and power management franchise with a proven technology portfolio and impressive history of empowering design innovation. Together, we are well-positioned to deliver the next wave of semiconductor growth, while engineering a healthier, safer and more sustainable future for all.”

“For over three decades, we have based Maxim on one simple premise – to continually innovate and develop high-performance semiconductor products that empower our customers to invent. I am excited for this next chapter as we continue to push the boundaries of what’s possible, together with ADI. Both companies have strong engineering and technology know-how and innovative cultures. Working together, we will create a stronger leader, delivering outstanding benefits to our customers, employees and shareholders,” said Tunç Doluca, President and CEO of Maxim Integrated.


Wednesday, June 17, 2020

Rambus delivers 112G XSR/USR PHY on TSMC 7nm

Rambus announced the availability of its 112G XSR/USR PHY based on TSMC’s industry-leading 7nm process.

Applications for the 112G XSR/USR PHY  and chiplet architectures include next-generation 51.2 Terabit per second (Tbps) ASICs for network switches, where 112G XSR links will connect the digital switch ASIC die to CPO engines. In AI/ML and HPC SoCs, the 112G XSR PHY can be used to bridge purpose-built accelerator chiplets for natural language processing, video transcoding and image recognition. Another popular use case is the die disaggregation of large SoCs, hitting reticle size limits for manufacturable yields, into multiple smaller die connected using XSR links over organic substrate. Increasingly, these advanced applications are implemented on TSMC’s N7 process.

“This important milestone highlights Rambus’ leadership in high-speed SerDes enabling the industry’s highest value and most demanding applications,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “At an industry-leading power efficiency of sub-picojoule per bit, and unidirectional bandwidth approaching two terabit per second per millimeter, we are very proud to offer our 112G XSR/USR solution in partnership with TSMC.”

“We’re pleased with the availability of Rambus’ PHY on our N7 process technology to address the growing market need for low-power, high-performance chiplet architectures,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “Our ongoing partnership with Rambus ensures that designers can meet next-generation requirements for performance and power efficiency in computing, AI/ML and networking using TSMC’s advanced process technologies.”

https://www.rambus.com/interface-ip/serdes/112g-xsr-phy

Monday, June 15, 2020

Intel announces Control-Flow Enforcement Technology

Intel is introducing a new security capability in its silicon microarchitecture to help protect against common malware attack methods that have been a challenge to mitigate with software alone.

Intel's new Control-Flow Enforcement Technology (Intel CET), which will be first available on Intel’s upcoming mobile processor code-named "Tiger Lake," is designed to protect against the misuse of legitimate code through control-flow hijacking attacks – widely used techniques in large classes of malware.

Intel CET offers software developers two key capabilities to help defend against control-flow hijacking malware: indirect branch tracking and shadow stack. Indirect branch tracking delivers indirect branch protection to defend against jump/call-oriented programming (JOP/COP) attack methods. Shadow stack delivers return address protection to help defend against return-oriented programming (ROP) attack methods. These types of attack methods are part of a class of malware referred to as memory safety issues and include tactics such as the corruption of stack buffer overflow and use-after-free.

Microsoft's support Intel CET in Windows 10 is called Hardware-enforced Stack Protection, and a preview of it is available today in Windows 10 Insider Previews. This new Hardware-enforced Stack Protection feature only works on chipsets with Intel CET instructions. It relies on a new CPU architecture that is compliant with Intel CET specifications. For applications running on an OS that supports Intel CET, users can expect detailed guidance from our partners on how applications “opt-in” for protection.

Thursday, June 11, 2020

AWS launches EC2 instances powered by its own Graviton2 processor

Amazon Web Services announced the general availability of its sixth generation of Amazon Elastic Compute Cloud (Amazon EC2) instances with three new instances powered by AWS-designed, Arm-based Graviton2 processors.

Graviton2 is a custom AWS design that is built using a 7nm manufacturing process and based on 64-bit Arm Neoverse cores. AWS says it can deliver up to 7x the performance of the A1 instances, including twice the floating point performance. Additional memory channels and double-sized per-core caches speed memory access by up to 5x.

The new general purpose (M6g), compute-optimized (C6g), and memory-optimized (R6g) instances deliver up to 40% better price/performance over comparable current generation x86-based instances. These sixth generation Amazon EC2 instances include:

  • M6g instances: designed for general-purpose workloads with balanced compute, memory, and networking, such as application servers, mid-size databases, microservices, and caching fleets.
  • C6g instances: designed for compute-intensive workloads, such as high performance computing, batch processing, video encoding, gaming, scientific modeling, distributed analytics, ad-serving, and CPU-based machine learning inference.
  • R6g instances: designed for workloads that process large data sets in memory, such as open source databases (MySQL, MariaDB, and PostgreSQL) or in-memory caches (Redis, Memcached, and KeyDB), and real-time big data analytics.

AWS said its Arm-based Amazon EC2 instances powered by Graviton processors are optimized for running scale-out workloads (e.g. containerized microservices and web tier applications).

“Today more than ever, customers are looking for innovative ways to increase performance and reduce cost, and Arm processors have emerged as an exciting and mainstream alternative to x86 processors for a wide variety of existing and emerging workloads,” said David Brown, Vice President, Amazon EC2, at AWS. “The new Amazon EC2 instances powered by AWS-designed, Arm-based, Graviton2 processors represent a significant generational leap for customers, delivering 40% better price/performance over comparable x86-based instances, and already we’ve seen a broad set of customers embrace them across a wide variety of general purpose, compute optimized, and memory optimized workloads.”
  • Netflix is using Amazon EC2 M instance types for a number of workloads, including streaming, encoding, data processing, and monitoring applications.


Wednesday, June 10, 2020

Intel launches "Lakefield" processors for ultralight devices

Intel introduced its "Lakefield" series of process for ultra small factors PC devices with single, dual, or foldable screens.

Intel said the new processors deliver full Windows 10 application compatibility in up to a 56% smaller package area for up to 47% smaller board size and extended battery life.

The new Intel Core processors with Intel Hybrid Technology leverage the company's Foveros 3D packaging technology and feature a hybrid CPU architecture for power and performance scalability.

“Intel Core processors with Intel Hybrid Technology are the touchstone of Intel’s vision for advancing the PC industry by taking an experience-based approach to designing silicon with a unique combination of architectures and IPs. Combined with Intel’s deepened co-engineering with our partners, these processors unlock the potential for innovative device categories of the future,” states Chris Walker, Intel corporate vice president and general manager of Mobile Client Platforms.

Tuesday, May 26, 2020

Samsung Electronics intros stand-alone security chip for mobiles

Samsung Electronics Co. introduced a Secure Element (SE) chip and enhanced security software for mobile devices that offers protection for tasks such as booting, isolated storage, mobile payment and other applications. The latest security chip is Common Criteria Evaluation Assurance Level (CC EAL) 6+ certified, the highest level acquired by a mobile component.

“In this era of mobility and contact-less interactions, we expect our connected devices, such as smartphones or tablets, to be highly secure so as to protect personal data and enable fintech activities such as mobile banking, stock trading and cryptocurrency transactions,” said Dongho Shin, senior vice president of System LSI marketing at Samsung Electronics. “With the new standalone security element solution (S3FV9RR), Samsung is mounting a powerful deadbolt on smart devices to safeguard private information.”

Samsung’s new security solution supports hardware-based root of trust (RoT), secure boot and device authentication that brings mobile security to the next level. Especially for service providers, manufacturers and organizations, secure device authentication is enhanced with the RoT when running proprietary applications on a mobile device. As a bootloader initiates, a chain of trust is activated through which each and every firmware with approved keys is sequentially validated. This secure booting process is handled by the RoT, guarding the device against any possible malicious attacks or unauthorized software updates.

Kyoto Semiconductor intros Two-Wavelength Photodiode

Kyoto Semiconductor Co. introduced a Two-Wavelength Photodiode with photosensitivity for a wide range of wavelengths, from 400 to 1,700 nm, arrayed along the same light axis. The device is capable of being surface-mounted, with silicon and indium-gallium-arsenide photodiodes. Samples will be available from August 31, 2020.

Applications could include spectroscopic analysis, enabling the identification of objects and their characteristics by reflecting light off those objects and measuring the degrees of transmission and reflection.

https://www.kyosemi.co.jp/en/lp/kpmc29

Monday, May 25, 2020

GLOBALFOUNDRIES adopts ITAR security and export control at Fab8

GLOBALFOUNDRIES will implement export control security measures at its most advanced manufacturing facility, Fab 8, in Malta, New York.

Specifically, the company plans to bring its Fab 8 facility into compliance with both the U.S. International Traffic in Arms Regulations (ITAR) standards and the Export Administration Regulations (EAR), making the company the most advanced ITAR foundry in the United States.

The new control assurances, which will go into effect later this year, will make confidentiality and integrity protections available for defense-related applications, devices or components manufactured at GF’s Fab 8 facility.

GF notes that it has invested over $13 billion in Fab 8 to date.


Wednesday, May 20, 2020

Samsung plans additional 5nm capacity at new fab in Pyeongtaek

Samsung Electronics will boost foundry capacity at the company's new production line in Pyeongtaek, Korea. The new foundry line will focus on EUV-based 5 nanometer (nm) and below process technology. Construction began this month and is expected to be in full operation in the second half of 2021.

Samsung recently added a new EUV-dedicated V1 line to its fab in Hwaseong, Korea. Initial mass production of the EUV-based 7nm process started in early 2019.  The company is on track to start mass production of 5nm EUV process in the Hwaseong fab in the second half of this year.

“This new production facility will expand Samsung’s manufacturing capabilities for sub-5nm process and enable us to rapidly respond to the increasing demand for EUV-based solutions,” said Dr. ES Jung, President and Head of Foundry Business at Samsung Electronics. “We remain committed to addressing the needs of our customers through active investments and recruitment of talents. This will enable us to continue to break new ground while driving robust growth for Samsung’s foundry business.”

With the addition of the Pyeongtaek fab, Samsung will have a total of seven foundry production lines located in South Korea and the United States, comprised of six 12-inch lines and one 8-inch line.