Showing posts with label Silicon. Show all posts
Showing posts with label Silicon. Show all posts

Thursday, January 23, 2020

Deutsche Telekom certifies Sequans' LTE-M

Sequans Communications' dual-mode LTE-M/NB-IoT Monarch chip and its Monarch-based module have been certified for LTE-M by Deutsche Telekom.

“Being certified by Deutsche Telekom is very important to our customers building LTE-M devices for Europe, and we are pleased to have the stamp of approval from Deutsche Telekom for our Monarch platform,” said Georges Karam, Sequans CEO. “Monarch is now certified by many carriers worldwide and our customers will benefit from this proven maturity as they build low power IoT devices for global use. Also the certification of our Monarch GM01Q module, which includes an LTE-optimized transceiver and a Single-SKU™ RF front end, further accelerates the time to market for new IoT devices.”

Tuesday, January 21, 2020

Sequans opens 5G design center in Israel

Paris-based Sequans Communications S.A. announced the expansion of its research and development resources in Israel with the opening of a new design center for the purpose of accelerating Sequans’ 5G new product development.

Sequans' new team is mainly focused on the development of 5G broadband and critical IoT products that will complement its existing massive IoT products, including the company’s flagship Monarch and Calliope platforms. The 5G products Sequans is readying for production include its 5G-compliant Monarch 2 LTE-M/NB-IoT chip announced in 2019 that will address the massive IoT market, and the coming new Taurus 5G chip that will address the broadband and critical IoT markets.

“Our new R&D center in Israel has been established to accelerate our ongoing 5G development and is a reflection of our commitment to keep our IoT products at the leading edge with best-in-class performance and lowest cost,” said Georges Karam, Sequans CEO. “Our 5G knowledge will be leveraged and augmented by this new team of experts who will ensure that we get across the goal line and get our new 5G products to market according to plan.”

Tuesday, January 14, 2020

Gartner: Worldwide semiconductor revenue drops 11.9% in '19

Worldwide semiconductor revenue totaled $418.3 billion in 2019, down 11.9% from 2018, according to preliminary results by Gartner, Inc. The report cites the drop in the memory market as the top reason for the decline. Sales analog products’ declined 5.4% while optoelectronics grew 2.4%.

“The memory market, which accounted for 26.7% of semiconductor sales in 2019, experienced a 31.5% decline in revenue in 2019,” said Andrew Norwood, research vice president at Gartner. “Within memory, DRAM revenue declined 37.5% due to an oversupply that started at the end of 2018 and lasted throughout 2019. The oversupply was caused by a sudden fall in demand from the hyperscale market. This revealed excessive OEM inventory levels that took the first half of the year to correct. Excessive inventory at DRAM vendors in the second half of 2019 pushed pricing lower and resulted in an average selling price (ASP) decline of 47.4% in 2019.”

“In 2020, we expect to see semiconductor market revenue increase after the high inventory clearance to drive up the chip ASP, especially in the memory sector,” said Mr. Norwood. “The U.S.-China trade war seems to be easing as we move into 2020. However, during 2019 the U.S. added several Chinese companies, including Huawei, to the Entity List restricting the sale of U.S. components. The immediate impact was to push Huawei into looking outside the U.S. for alternative silicon suppliers, with wholly owned HiSilicon at the top of the list as well as alternative suppliers based in Japan, Taiwan, South Korea and China. This will be an area to watch in 2020.”

Tuesday, December 17, 2019

Samsung readies production of Baidu's KUNLUN AI silicon

Baidu’s first cloud-to-edge AI accelerator chip has completed development and will be mass-produced early next year by Samsung Electronics.

Baidu KUNLUN chip is built on the company’s advanced XPU, a home-grown neural processor architecture for cloud, edge, and AI, as well as Samsung’s 14-nanometer (nm) process technology with its I-Cube (Interposer-Cube) package solution.

The chip offers 512 gigabytes per seconds (GBps) memory bandwidth and supplies up to 260 Tera operations per second (TOPS) at 150 watts. In addition, the new chip allows Ernie, a pre-training model for natural language processing, to inference at three times faster than that of conventional GPU/FPGA-accelerating model.

“Baidu KUNLUN is an important milestone for Samsung Foundry as we’re expanding our business area beyond mobile to datacenter applications by developing and mass-producing AI chips. Samsung will provide comprehensive foundry solutions from design support to cutting-edge manufacturing technologies, such as 5LPE, 4LPE, as well as 2.5D packaging.”

“We are excited to lead the HPC industry together with Samsung Foundry,” said OuYang Jian, Distinguished Architect of Baidu. “Baidu KUNLUN is a very challenging project since it requires not only high level of reliability and performance at the same time, but is also a compilation of the most advanced technologies in the semiconductor industry. Thanks to Samsung's state of the art process technologies and competent foundry services, we were able to meet and surpass our goal to offer superior AI user experience.”

“We are excited to start a new foundry service for Baidu using our 14nm process technology,” said Ryan Lee, vice president of Foundry Marketing at Samsung Electronics. “Baidu KUNLUN is an important milestone for Samsung Foundry as we’re expanding our business area beyond mobile to datacenter applications by developing and mass-producing AI chips. Samsung will provide comprehensive foundry solutions from design support to cutting-edge manufacturing technologies, such as 5LPE, 4LPE, as well as 2.5D packaging.”

Wednesday, December 11, 2019

The design philosophy of Cisco Silicon One



About 5 years ago, Cisco set out to design a new silicon architecture, one which could serve multiple markets and scale over time.

Eyal Dagan, SVP Silicon, Cisco, shares his views on the design philosophy of Cisco Silicon One. It was a clean sheet approach. A key question -- is it possible to create a routing chip with the efficiency of switching silicon?

https://youtu.be/P5QwOKaxRtI



The 400G-ZR Transition



400G-ZR is going to shift network architectures, says Bill Gartner, SVP/GM of Cisco's Optical Systems and Optics Group. Many customers will continue to deploy chassis solutions, but others will choose pluggables in a router for coherent transmission.

Cisco is also discussing the changing consumption models for network silicon and optics as some customers seek fully disaggregated solutions.

https://youtu.be/RrKqRv8-7po

Broadcom ships its 25.6 Tbps Tomahawk 4

Broadcom has begun commercial shipments of its 25.6 Tbps StrataXGS Tomahawk 4 Ethernet switching silicon -- representing double the bandwidth of any other switch silicon currently on the market.

The 25.6 Tbps capacity enables port densities of up to 64 × 400GbE, 128 × 200GbE, 256 × 100GbE, 256 × 40GbE, 256 × 25GbE, or 256 × 10GbE ports.

Tomahawk 4, which is implemented in 7nm technology with 512 50G PAM4 SerDes, arrives less than two years after the previous 12.8Tbps product generation.

Tomahawk 4 is designed for the backbone for the next generation of hyperscale data center networks.

Broadcom said its Tomahawk 4 accelerates the adoption of 100/200/400GbE Ethernet solutions at a point where optics utilizing 50G PAM4 electrical connectivity are shipping in high volumes.

“The Tomahawk franchise is the flagship for cutting-edge, single-chip performance and integration among Broadcom’s multi-vectored Ethernet switch silicon portfolio, tailored to the unique and rigorous demands of hyperscale data center operators,” said Ram Velaga, senior vice president and general manager, Core Switching Group, Broadcom. “We are proud of our world-class engineering team for innovating and delivering the 25.6Tbps Tomahawk 4 chip in less than two years after we released Tomahawk 3.  Broadcom is proving yet again that customers can rely on us to lead the industry on switch silicon performance and execution at every generation.”

Key points for StrataXGS Tomahawk 4:

  • Enables the next generation of high-throughput, low latency hyperscale networks with 64 ports of 400GbE switching and routing.
  • World’s highest radix of 100GbE ports: 256 ports supported on a single chip, enabling low-latency, single-hop networks for massive alternative compute clusters.
  • Robust connectivity using 512 instances of the industry’s highest performance and longest-reach 50G PAM4 SerDes core, enabling long-reach East-West optical links and Direct-Attached-Copper in-rack cabling in the data center.
  • The industry’s most advanced 25.6Tbps shared-buffer architecture, offering up to 5X higher incast absorption and providing the highest performance and lowest end-to-end latency for RoCEv2 workloads.
  • New advanced load balancing mechanisms, virtually eliminating hash polarization and providing extremely efficient, controllable link utilization.
  • Advanced congestion management, enabling new traffic management paradigms.
  • Industry-leading instrumentation including IFA 2.0 for inband telemetry, postcards for out-of-band telemetry, SerDes link quality meters, and visibility into all on-chip packet drops and congestion events.
  • Four 1 GHz ARM processors for high-bandwidth, fully-programmable streaming telemetry and sophisticated embedded applications such as on-chip statistics summarization.
  • Implemented in a monolithic 7nm die.


Broadcom also announced the introduction of Broadcom Open Network Switch APIs (OpenNSA), opening its SDK APIs for StrataXGS and StrataDNX products. Multiple open source network operating system initiatives are underway in the disaggregation ecosystem, focused on hyperscale and service provider markets. OpenNSA enables these initiatives on merchant silicon and allows the larger community to build on top of these efforts. OpenNSA also expands Open Compute Project efforts, like Switch Abstraction Interface (SAI), by simplifying the process of translating SAI APIs to Broadcom SDK APIs. Moreover, OpenNSA accelerates the SDN ecosystem by enhancing the toolset available for the developer community.

https://www.broadcom.com/products/ethernet-connectivity/switching/strataxgs/bcm56990-series

Tuesday, December 10, 2019

Lattice intros low-power FPGAs

Lattice Semiconductor introduced its new low power FPGA platform, Lattice Nexus, which targets applications such as AI for IoT, video, hardware security, embedded vision, 5G infrastructure and industrial/automotive automation.

The Lattice Nexus platform features optimized DSP blocks and higher on-chip memory capacity to enable power-efficient computing, such as AI inferencing algorithms, and runs twice as fast at half the power of Lattice’s previous FPGAs. Lattice Nexus also uses innovative circuit design to deliver key capabilities to customers, including programmable power-performance optimization and very fast configuration for instant-on type applications.

Lattice Nexus is developed on high-volume 28 nm fully-depleted silicon-on-insulator (FD-SOI) process technology from Samsung. This innovative technology features 50 percent lower transistor leakage compared to bulk CMOS, and is the best technology for delivering the low power Lattice Nexus platform.

“The Lattice Nexus platform augments the parallel processing and re-programmability of FPGAs with the power-efficient performance demanded by today’s technology trends, like AI inferencing at the Edge and sensor management. The platform also accelerates the rate at which Lattice will release future products,” said Steve Douglass, Corporate Vice President, R&D, Lattice Semiconductor. “Additionally, the Lattice Nexus platform offers easy-to-use solution stacks targeting high-growth applications that help customers more quickly develop their systems, even if they are not expert in FPGA design.”

www.latticesemi.com/LatticeNexus

Monday, December 9, 2019

Andes' RISC-V processor qualified for Amazon FreeRTOS

Andes Technology's Corvette-F1 N25 platform is one of the first RISC-V platforms qualified for Amazon FreeRTOS.

Amazon FreeRTOS is an open source operating system for microcontrollers from Amazon Web Services (AWS) designed for small, low-power edge devices.

“IoT, and AIoT, will be a big addressable market for RISC-V CPU,” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “By leveraging the advantages of Amazon FreeRTOS and Andes RISC-V platform, we can provide developers using Amazon FreeRTOS additional development platform choices and strengthen the Andes RISC-V IoT solutions for our customers.”

Andes' Corvette-F1 N25 platform is a FPGA-based Arduino-compatible evaluation platform. It comes with a 32-bit RISC-V AndesCore N25 running at 60MHz, 4MB Flash, 256KB instruction SRAM and 128KB data SRAM, and AndeShape AE250 Platform IP with rich peripherals such as GPIO, I2C, PWM, SPI, and UART. It also contains an on-board wireless module supporting IEEE 802.11 b/g/n.

http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-n25/

Cambium adopts Sequans’ LTE-Advanced chipset for CPE

Cambium Networks has adopted Sequans’ LTE-Advanced chipset platform, Cassiopeia, for two Customer Premises Equipment (CPE) designs for global markets. Both are high-performance integrated access devices with which Cambium Networks aims to meet the integrated data, voice, and internet access needs of its residential, business, and enterprise customers.

  • cnRanger 2 GHz Tyndall 101. An LTE Category 4 Subscriber Module with 14 dBi integrated panel antenna supporting TD-LTE Bands 38, 40 and 41. Available now.
  • cnRanger 3 GHz Tyndall 201. An LTE Category 6 Subscriber Module with 19 dBi integrated dish antenna supporting TD-LTE Bands 42, 43 and 48. Available mid-2020.

The LTE-Advanced chip inside the new Cambium Networks CPE devices is Sequans’ Cassiopeia LTE-Advanced chip platform, a member of Sequans’ StreamrichLTE family of products for broadband high-performance devices. Cassiopeia is compliant with 3GPP Release 10 specifications and supports highly flexible dual-carrier aggregation that allows the combination of any two carriers of any size up to 20 MHz each, contiguous or non-contiguous, inter-band or intra-band. Cassiopeia also supports other Release 10 enhancements such as new MIMO schemes, enhanced inter-cell interference coordination (eICIC) schemes for heterogeneous networks (HetNets), and improvements to eMBMS (evolved multimedia broadcast multicast service) or LTE broadcast. Cassiopeia features Sequans’ advanced receiver technology for improved performance.

Wednesday, December 4, 2019

Qualcomm packs a punch with its Snapdragon 865 5G

Qualcomm unveiled its latest flagship mobile chipset- the Snapdragon 865 5G Mobile Platform, which combines an advanced 5G Modem-RF System with the processing capabilities to power the next generation of flagship mobile devices.

At a media event in Hawaii, Qualcomm execs previewed camera, audio, and gaming experiences that made possible by the whopping 15 TOPS of AI performance delivered by the new 7nm chipset. This includes the option for real-time translations of a phone conversation to another language. Imaging possibilities include the ability to capture in 4K HDR with over a billion shades of color, capture 8K video, or snap massive 200-megapixel photos.

Snapdragon 865 5G highlights:

  • Compatible with both 5G standalone and non-standalone modes  
  • Multi-gigabit downlink speeds of up to 7.5 Gbps 
  • Support for all key regions and frequency bands from 5G mmWave and sub-6, TDD and FDD, to SA and NSA modes
  • Dynamic Spectrum Sharing (DSS)
  • 5G mmWave specs: 800 MHz bandwidth, 8 carriers, 2x2 MIMO
  • 5G sub-6 GHz specs: 200 MHz bandwidth, 4x4 MIMO
  • LTE including CBRS support
  • 5th generation Qualcomm AI Engine packs 2x the performance of its predecessor. Qualcomm Hexagon Tensor Accelerator pushes 15 trillion operations per second
  • Dolby Vision video capture
  • 8K video recording
  • 200 megapixel photos
  • Simultaneously captures 4K HDR video and 64 MP photos
  • Qualcomm Sensing Hub ensures highly accurate voice detection and always-on contextual awareness for smarter virtual assistants
  • Qualcomm Adreno 650 GPU delivers up to 25% performance boost from its predecessor
  • Wi-Fi Standards: 802.11ax (Wi-Fi 6), 802.11ax (Wi-Fi 6-ready), 802.11ad, 802.11ay, 802.11ac Wave 2, 802.11a/b/g, 802.11n
  • Qualcomm Wi-Fi 6 technology features: MU-MIMO (Uplink and Downlink), 8x8 sounding, OFDMA (Uplink and Downlink), 1024 QAM, Dual-band simultaneous (DBS), WPA3 security support, Target Wake Time
  • Bluetooth 5.1
  • USB 3.1, USB-C


“Snapdragon 865 supports the world’s most advanced 5G connectivity and features, raising the bar for what a mobile device should be,” said Alex Katouzian, senior vice president and general manager, mobile, Qualcomm Technologies, Inc. “It’s the culmination of Qualcomm’s more than 30 years of wireless leadership and innovation.”

https://www.qualcomm.com/products/snapdragon-865-5g-mobile-platform

Tuesday, December 3, 2019

AWS previews EC2 instances running its own Graviton2 processors

AWS offered a sneak peek at its next generation of Arm-based EC2 instances powered by its own Graviton2 processor.

Graviton2 is a custom AWS design that is built using a 7nm manufacturing process and based on 64-bit Arm Neoverse cores. AWS says it can deliver up to 7x the performance of the A1 instances, including twice the floating point performance. Additional memory channels and double-sized per-core caches speed memory access by up to 5x.

AWS estimates up to 40% better price performance over comparable current generation instances for a wide variety of workloads, including application servers, micro-services, high-performance computing, electronic design automation, gaming, open-source databases, and in-memory caches.

Graviton2 will be able to run Amazon Linux 2, Red Hat Enterprise Linux, Ubuntu, SUSE Linux Enterprise Server, Fedora, FreeBSD, and Debian. Container support includes Docker, Amazon Elastic Kubernetes Service, Amazon Elastic Container Service, and Firecracker.

https://aws.amazon.com/ec2/graviton/

Sunday, December 1, 2019

Panasonic sells its semiconductor group to Taiwan's Nuvoton

Panasonic Corporation will transfer its semiconductor business to Taiwan-based Nuvoton Technology, a division of Winbond, in an all-cash transaction. Financial terms were not disclosed.

Panasonic Semiconductor Solutions, located in Nagaokakyo City, Kyoto, is a leading global supplier of semiconductor devices and solutions with products that focus on “Sensing” technologies such as Image Sensors, Image / Digital Signal Processors, “Microcontroller” technologies such as MCU, IC Card, Battery Management, Power Management and ”Component” technologies such as MOSFET, RF-GaN and Laser Diode.

Panasonic said it decided to exit semiconductors due to the aggressive expansion of competitors that would require huge investments to keep up.

Thursday, October 24, 2019

Intel intros Tremont microarchitecture

Intel unveiled Tremont, its next-generation, low-power x86 microarchitecture promising significant IPC (instructions per cycle) gains gen-over-gen compared with Intel’s prior low-power x86 architectures.

Tremont is aimed at compact, low-power packages and innovative form factors for client devices, creative applications for the internet of things (IoT), data center products, etc.

Tremont is integrated within a wider set of silicon IPs in Lakefield, which will power innovative devices like the recently announced dual-screen Microsoft Surface Neo. Iy includes several advancements in ISA (instruction set architecture), microarchitecture, security and power management. Specifically, Tremont’s unique 6-wide (2x3-wide clustered) out-of-order decoder in the front end allows for a more efficient feed to the wider back end, which is fundamental for performance.

The announcement was made at this week's Linley Fall Processor Conference 2019 in Silicon Valley.

https://newsroom.intel.com/wp-content/uploads/sites/11/2019/10/introducing-intel-tremont-microarchiture.pdf

Monday, October 14, 2019

Metanoia updates its Gfast chipset

Metanoia Communications, a subsidiary of Elan Microelectonics based in Taiwan and developer of high-speed xDSL and Gfast PHY chipsets for wireline broadband applications, introduced its latest family of chipsets that supports all the ITU-T Gfast (212MHz profile) and VDSL2 (35MHz profile) standards and builds on Metanoia’s existing Gfast, VDSL2 and ADSL2/2+ technology. With its MT-x2331 product family, Metanoia will deliver the industry first next generation broadband access xDSL PHY chipset for multiple applications including home gateways, low density xDSL Central Office systems and standalone xDSL termination, such as SFP modules.

Metanoia MT-x2331 series is a chipset family that supports all existing ITU-T Gfast, VDSL2 and ADSL2/2+ standards. Each member of the family, namely, the MT-V2331 (VDSL2 only), the MT-G2331 (Gfast only) and the MT-C2331 (for both G.fast and VDSL2), comprises a DMT (Discrete Multi-Tone) chip and an AFE (Analog Front End) chip, each in a single small package, thereby greatly minimizing the board size to meet the requirements and form factors of a wide variety of different applications.

“Bringing this new programmable architecture to life enables us to deliver a unique low power and highly integrated xDSL PHY solution with future-proof capabilities for the Operators to upgrade their WAN solutions in the field as standards and requirements develop,” added Didier Boivin, executive vice president at Metanoia Communications. “Our combined product offering with NXP will enable customers to address all xDSL market segments, starting from a simple single-port PHY to a sophisticated high-end home gateway with WiFi capabilities, using the same core xDSL technology.”

http://www.metanoia-comm.com/

Tuesday, October 8, 2019

Nokia aims Quillion chipset at next gen access

Nokia outlined plans for a new family of chipsets to power next-generation massive scale access networks.

The forthcoming "Quillion" chipset will allow operators to introduce 10G PON in their fiber networks and to serve more users from G.fast access nodes. For next-generation fiber access networks, the Quillion chipset powers Nokia’s 16-port Multi-PON line card, which supports both GPON and NG-PON on each port. This allows operators with an existing GPON network to simply “switch on” NG-PON services on each port without recabling or disrupting the GPON service.

Nokia said Quillion is also optimized to allow for low-latency applications that are critical for 5G transport and has built-in programmability to support intents that pave the way toward automated workflows, such as network slicing for 5G transport.

In addition, the Quillion chipset supports copper infrastructure access, including the highest density G.fast and Vplus solutions on the market.

Sandra Motley, President of Fixed Networks at Nokia, said: “In a 5G world, consumers will expect a gigabit experience regardless if they are at home or on the go. Our Quillion chipset is designed to deliver gigabit broadband to every home, using  broadband technologies like fiber to complement 5G in massive scale access networks. This allows operators to efficiently connect more people with higher speeds, and positively impacts their business case.”

Arm to support custom instructions for Cortex CPUs

Arm will introduce a new custom instructions feature for its Armv8-M architecture. The approach gives chip designers the ability to add unique application-specific features into Cortex-M33 CPUs.

Arm Custom Instructions will initially be implemented in Arm Cortex-M33 CPUs starting in the first half of 2020 at no additional cost to new and existing licensees, enabling SoC designers to add their own instructions for specific embedded and IoT applications without risk of software fragmentation.

“A world of a trillion secure intelligent devices will be built on a diversity of complex use cases requiring increased synergy between hardware and software design,” said Dipti Vachani, senior vice president and general manager, Automotive and IoT Line of Business, Arm. “We have engineered Arm Custom Instructions to fuel closer hardware and software co-design efforts toward achieving application-specific acceleration while unlocking greater device differentiation.”

https://www.arm.com/company/news/2019/10/arm-enables-custom-instructions-for-embedded-cpus

Tuesday, September 3, 2019

Semtech debuts XGSPON chipset

Semtech announced production availability of itsGN7153B combo chip and GN7055B multi-rate burst mode transimpedance amplifier (TIA) for XGSPON Optical Line Terminals (OLTs).

Semtech's GN7153B is a combo chip supporting OLT transmit and receive signals in a fully integrated solution.

On the receive side, the GN7153B supports both XGPON (2.5G) and XGSPON (2.5G/10G) signals, while the transmit data path features Semtech’s 10G EML driver with ClearEdge CDR technology to effectively reset the signal jitter budget. Transmit path optimization can be accomplished through an I2C programmable PLL loop bandwidth control and a variety of jitter filter modes. The EML driver includes eye-shaping features and an Automatic Power Control (APC) loop to deliver best-in-class transmit eye quality. The burst mode receive data path includes a multi-rate 2.5G/10G limiting amplifier with a fast burst mode signal detect function, integrated discharge circuit and reset for short settling time.

Semtech said its high sensitivity burst mode TIA (GN7055B) is designed for XGSPON OLT applications. Using an external reset signal, the burst mode TIA meets the convergence time and burst dynamic range requirements of XGSPON 2.5G and 10G.The device features a fast Automatic Gain Control (AGC) loop to enable high dynamic range in burst mode applications. The GN7055B is offered in die form, supports industrial temperature range and uses a single 3.3V power supply.

“XGSPON will bring a new generation of faster optical broadband services for home and business to the largest sector of the PON market,” said Dr. Timothy Vang, Vice President of Marketing and Applications for Semtech’s Signal Integrity Products Group. “Our chipset contributes to that growth by bringing high performance and low cost.”

http://www.semtech.com/optical

Wednesday, August 21, 2019

Xilinx's Virtex UltraScale+ FPGA boasts 35 billion transistors

Xilinx has expanded its 16nm Virtex UltraScale+ family to now include the world's largest FPGA — the Virtex UltraScale+ VU19P.

The new VU19P FPGA boasts 35 billion transistors, the highest logic density and I/O count on a single device, according to Xilinx. The device could be used for enabling emulation and prototyping of tomorrow's most advanced ASIC and SoC technologies, as well as test, measurement, compute, networking, aerospace and defense-related applications.

The VU19P FPGA features 9 million system logic cells, up to 1.5 terabits per-second of DDR4 memory bandwidth and up to 4.5 terabits per-second of transceiver bandwidth, and over 2,000 user I/Os. It is 1.6X larger than its predecessor and what was previously the industry's largest FPGA — the 20 nm Virtex UltraScale 440 FPGA. 

"The VU19P enables developers to accelerate hardware validation and begin software integration before their ASIC or SoC is available," said Sumit Shah, senior director, product line marketing and management, Xilinx. "This is our third generation of world-record FPGAs. First was the Virtex-7 2000T, followed by the Virtex UltraScale VU440, and now the Virtex UltraScale+ VU19P. But this is more than silicon technology; we're providing robust and proven tool flows and IP to support it."

"Arm relies on Xilinx devices as part of our process for validating our next-generation processor IP and SoC technology," said Tran Nguyen, director of design services, Arm. "The new VU19P will further enable Arm, and many others in our ecosystem, to accelerate the design, development and validation of our most ambitious roadmap technologies."

The VU19P will be generally available in the fall of 2020.

https://www.xilinx.com/news/press/2019/xilinx-announces-the-world-s-largest-fpga-featuring-9-million-system-logic-cells.html

Monday, August 19, 2019

Cerebras Wafer Scale Engine packs 1.2 trillion transistors

Cerebras, a start-up based in Los Altos, California, unveiled its Wafer Scale Engine - a record-setting AI processor boasting a die size of 46,225 square millimeters and containing more than 1.2 trillion transistors. The chip is 56X larger than the largest graphics processing unit and contains 3,000X more on-chip memory.

Key specs

  • 400,000 Sparse Linear Algebra (SLA) cores
  • 18GB on-chip SRAM, all accessible within a single clock cycle, and provides 9 PB/s memory bandwidth. 
  • 100 Pb/s interconnect bandwidth in a 2D mesh
  • Manufactured by TSMC on its 16nm process technology

The SLAC cores are flexible, programmable, and optimized for the sparse linear algebra, which underpins neural network computation. The cores are linked together with a fine-grained, all-hardware, on-chip mesh-connected communication network called Swarm.

“Designed from the ground up for AI work, the Cerebras WSE contains fundamental innovations that advance the state-of-the-art by solving decades-old technical challenges that limited chip size—such as cross-reticle connectivity, yield, power delivery, and packaging,” said Andrew Feldman, founder and CEO of Cerebras Systems. “Every architectural decision was made to optimize performance for AI work. The result is that the Cerebras WSE delivers, depending on workload, hundreds or thousands of times the performance of existing solutions at a tiny fraction of the power draw and space.”

The Cerebras product unveiling occurred at this week's Hot Chips Conference at Stanford University.

http://www.cerebras.net

See also