Showing posts with label SerDes. Show all posts
Showing posts with label SerDes. Show all posts

Tuesday, November 17, 2020

Marvell announces first 112G 5nm SerDes

Marvell introduced the first 112G 5nm SerDes solution that has been validated in hardware. The company also confirmed that it has recently secured a new custom ASIC design win customer that will embed this new IP to build next generation top-of-rack (ToR) and spine switches for leading hyperscale data centers.

The Marvell 5nm SerDes solution doubles the bandwidth of current systems based on 56G while enabling the deployment of 112G I/Os. The device offers the ability to operate at 112G PAM4 across channels with >40dB insertion loss. The solution also delivers power reduction of more than 25% compared to 7nm, enabling systems with tight thermal/power constraints and helping to drive down total cost of ownership. The power reduction of Marvell's high-speed SerDes enables scale up of bandwidth within acutely constrained 5G applications.

Marvell plans to offer a complete product suite of PHYs, switches, data processor units (DPUs), custom server processors, controllers, accelerators and custom ASICs in 5nm, delivering end-to-end interoperable infrastructure solutions. This interoperability between Marvell components will allow customers to significantly reduce their product development and validation cycle time, and time-to-market.

"Our new 112G 5nm SerDes solution, with its industry-leading power, performance and area metrics is a true game changer and will help scale data infrastructure to meet growing interconnect requirements," said Sandeep Bharathi, senior vice president of Central Engineering at Marvell. "System performance is typically limited by bandwidth and power in most infrastructure applications, and our new 112G solution in 5nm addresses this by doubling the bandwidth, while reducing the overall I/O power."

"We are excited to bring this proven 112G SerDes to our custom ASIC partners looking for the highest throughput at the lowest power in the industry. Our customers in multiple markets have confirmed for us that this IP exceeds their system requirements for performance and power consumption," said Kevin O'Buckley, vice president and general manager of the ASIC BU at Marvell. "Leveraging this 5nm SerDes IP across our Marvell platform allows our customers to build entire interoperable data center, wireless and wired networking systems using Marvell standard products, customized standard products and full custom ASIC solutions."


Marvell to acquire Inphi for optical components business

Marvell Technology Group Ltd. agreed to acquire Inphi Corp. in a cash and stock transaction valued at approximately US$10 billion, consisting of $66 in cash and 2.323 shares of stock of the combined company for each Inphi share. Upon closing of the transaction, Marvell shareholders will own approximately 83% of the combined company and Inphi stockholders will own approximately 17% of the combined company.Inphi’s high-speed electro-optics target data...

Marvell intros a customizable ASIC program in 5nm

Marvell debuted a cutomizable ASIC targetting applications ranging from next generation 5G carriers, cloud data centers, enterprise and automotive. Marvell’s new ASIC solution enables a multitude of customization options and a differentiated approach with best-in-class standard product IP including Arm-based processors, embedded memories, high-speed SerDes, networking, security and a wide range of storage controller and accelerators in 5nm and below. With...


Monday, May 18, 2020

Cadence offers 56G Long-Reach PAM4 SerDes IP

Cadence Design Systems released 56G long-reach SerDes IP on TSMC’s N7 and N6 process technologies.

The company expects 56G connectivity to be particularly important for 5G infrastructure deployment, both in baseband and remote radio head systems. To address this broader market, Cadence has expanded its PAM4 SerDes portfolio with 56G long-reach SerDes IP on the TSMC N7 and N6 processes delivering optimized power, performance and area (PPA).

The Cadence 56G long-reach SerDes IP highlights:

  • Best-in-class 36db+ insertion loss using Cadence’s multi-rate DSP technology
  • Industrial temperature range, CPRI data rate support and per-lane PLL are ideal for 5G applications
  • 56G long-reach performance has been achieved on N7 test silicon and is compatible with the N6 process
  • Fully compliant with the IEEE standard specification
  • Programmable power configurations via a unique firmware-controlled adaptive power optimizer, which provides optimal power and performance tradeoffs and more efficient system designs based on platform requirements
  • Optimal data recovery through the programmable DSP-based architecture, which allows optimal power delivery for a given reach and provides superior data recovery under lossy and noisy channel conditions
  • Improved flexibility enabled by the extended reach capability lets customers use lower cost PCBs and achieve greater flexibility in PCB and system design

“We are pleased to see Cadence expand its PAM4 offerings to include 56G and extend support to TSMC N7 and N6 process technologies,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “This joint effort combining Cadence’s leading edge SerDes IP and TSMC’s advanced process technologies will help our customers unleash their silicon innovations for emerging 5G and hyperscale data center applications.”

“After being first to market in 2019 with silicon-proven 112G-LR SerDes on TSMC 7nm technology, we have now expanded our offering to include PPA-optimized 56G-LR to address the connectivity needs of the 5G infrastructure and AI/ML market. This new PAM4-based 56G-LR SerDes is based on Cadence’s well-proven multi-rate DSP technology,” said Rishi Chugh, vice president of product marketing, IP Group at Cadence. “The availability of Cadence’s 56G long-reach SerDes IP on the TSMC N7 and N6 processes accelerates the adoption and deployment of cost-effective 100G and 400G networks.”

http://www.cadence.com/go/56GSerDes

Thursday, January 17, 2019

Socionext to highlight 112G SerDes for 100G/200G/400G

Socionext will feature its advanced SoC designs including 112G SerDes, 120+ GS/s ADC/DAC, AI technology, high-performance memory, multi-die packaging and RF/mmWave solutions at DesignCon later this month at the Santa Clara Convention Center.

Socionext provides a high-performance SerDes macro with up to 112Gbps per channel for 100G/200G/400G networks. These capabilities are further extended by utilizing the company’s ultra-high-speed ADC & DAC technologies, a key component in coherent and direct detect optical networking SoCs enabling Terabit (Tbps) datacenter interconnect (DCI) solutions for hyperscale cloud operators.

Socionext will demonstrate solutions of ultra-energy-efficient 56Gb/s PAM4 SR to LR CMOS transceivers optimized to help companies cost-effectively meet the ever-increasing demand for performance, functionality and design requirements.

The company will also showcase a high-performance, energy-efficient edge server with AI accelerator delivering powerful parallel processing performance for video processing and image recognition. This video management system is optimized for facial and object recognition ideal for surveillance and security applications.
ments. Socionext will also showcase advanced “Chip-Package-PCB co-design” methodology developed to help companies quickly and cost-effectively deliver high-quality, high-performance, multi-die packaging and RF/mmWave solutions.