Showing posts with label Intel. Show all posts
Showing posts with label Intel. Show all posts

Thursday, October 21, 2021

Intel sees 10% rise in Data Center Group sales, except cloud

 Citing strong revenue for its Internet of Things Group (IOTG) and record third-quarter revenue in the Data Center Group (DCG) and Mobileye businesses, Intel reported Q3 GAAP revenue of $19.2 billion, up 5% year over year (YoY), and non-GAAP revenue of $18.1 billion, up 5% YoY. 

While topline revenue missed market estimates by $170 million, non-GAAP EPS surpassed expectations. Third-quarter GAAP earnings-per-share (EPS) was $1.67; non-GAAP EPS was $1.71, which exceeded July guidance by $0.61. As a result, Intel raised its full-year 2021 EPS and gross margin guidance and is now expecting GAAP EPS of $4.50 and non-GAAP EPS of $5.28 and GAAP gross margin of 55% and non-GAAP gross margin of 57%.

“Q3 shone an even greater spotlight on the global demand for semiconductors, where Intel has the unique breadth and scale to lead. Our focus on execution continued as we started delivering on our IDM 2.0 commitments. We broke ground on new fabs, shared our accelerated path to regain process performance leadership, and unveiled our most dramatic architectural innovations in a decade. We also announced major customer wins across every part of our business,” said Pat Gelsinger, Intel CEO. “We are still in the early stages of our journey, but I see the enormous opportunity ahead, and I couldn’t be prouder of the progress we are making towards that opportunity.”



Friday, September 24, 2021

Intel breaks ground on $20 billion fabs in AZ

Intel broke ground on two new fabs (52 and 62) at the company’s Ocotillo campus in Chandler, Arizona. When fully operational in 2024, the new fabs will manufacture Intel’s most advanced process technologies, including Intel 20A featuring the new RibbonFET and PowerVia innovations. The capacity is expected to be used for Intel's own products as well as for customers of the newly formed Intel Foundry Services.

“Today’s celebration marks an important milestone as we work to boost capacity and meet the incredible demand for semiconductors: the foundational technology for the digitization of everything. We are ushering in a new era of innovation – for Intel, for Arizona and for the world. This $20 billion expansion will bring our total investment in Arizona to more than $50 billion since opening the site over 40 years ago. As the only U.S.-based leading-edge chipmaker, we are committed to building on this long-term investment and helping the United States regain semiconductor leadership,” stated Pat Gelsinger, Intel CEO.



Tuesday, September 7, 2021

Intel eyes automotive silicon expansion

Intel CEO Pat Gelsinger predicts the “digitization of everything” will push the share of semiconductors in the total new premium vehicle bill of materials (BOM) to more than 20% by 2030 – up more than 5X from 4% in 2019. The company forecasts the total addressable market (TAM) for automotive silicon will more than double by the end of the decade to $115 billion – approximately 11% of the entire silicon market.2

In pursuit of this opportunity, Intel announced plans to build new chip manufacturing facilities in Europe, establish committed foundry capacity at its Ireland site, and launch the Intel Foundry Services Accelerator to help foundry customers move automotive designs to advanced nodes.

In addition, Intel's Mobileye division unveiled the first production AV equipped with the Mobileye Drive self-driving system and bearing the MoovitAV services branding. Mobileye is working with Sixt to bring autonomous ride-hailing into operation with Munich-based Sixt SE starting in 2022. 


https://www.intel.com/

Wednesday, September 1, 2021

Juniper integrates RAN Intelligent Controller with Intel FlexRAN

Juniper Networks is collaborating with Intel to accelerate advancement in the Open RAN (ORAN) ecosystem. The collaboration includes:

  • Juniper RAN Intelligent Controller (RIC) and Intel FlexRAN platform are pre-integrated and pre-validated to enhance usability of a full ORAN-compliant Intelligent RAN system
  • Collaborative R&D work with Intel Labs for RIC platform-specific apps to improve customer experience, maximize ROI and drive rapid ORAN ecosystem innovation
  • Joint customer testbeds with Intel to validate performance-improving implementation and speed of time-to-market

Earlier this year, Juniper announced an exclusive global licensing agreement with Netsia, a subsidiary of Türk Telekom Group company Argela in the USA. Netsia transferred its Radio Intelligent Controller (RIC) technology to Juniper, including related source code and patents plus exclusive rights to develop and sell products and solutions that integrate with RIC.  The deal included the transfer of technical domain experts from Netsia to Juniper in support of RIC’s integration into Juniper’s product portfolio. 


Juniper is an active member of the O-RAN Alliance, contributing to six working groups and serving as chair and co-chair of the slicing and use-case task groups, respectively. Juniper is also an editor of RIC specifications within the alliance.

Juniper said the joint initiative represents another milestone in its continuing efforts to bring openness and innovation to a traditionally closed-off part of the network, providing a faster route-to-market for service providers and enterprises to deliver 5G, edge computing and AI.

“Juniper has always been committed to open infrastructures, which is why we are excited to support the work that Intel has undertaken with their FlexRAN ecosystem. By collaborating with Intel, we are able to deliver cloud-native routing, automation, intelligence and assurance solutions and services that are optimized for our customers’ needs, speeding time-to-market and enabling them to monetize faster," stated Constantine Polychronopoulos, VP of 5G and Telco Cloud at Juniper Networks.

“The virtualization of the RAN continues to gain momentum across the industry as operators take advantage of cloud economics and the delivery of new services. This collaboration with Juniper and the validation of FlexRAN and RIC solutions will assist service providers to overcome integration challenges and accelerate time-to-market for future deployments," stated Caroline Chan, VP Intel Corporation, GM of Network Business Incubator Division.


Wednesday, August 25, 2021

Wind River and Intel collaborate on 5G vRAN for FlexRAN

 Wind River and Intel are jointly developing a 5G vRAN solution that integrates Intel FlexRAN reference software for systems powered by 3rd Gen Intel Xeon Scalable processors with built-in AI acceleration, and also features Intel Ethernet 800 Network Adapters and the Intel vRAN Dedicated Accelerator ACC100 in concert with Wind River Studio. 

The collaboration will further expand with future next-generation Intel Xeon Scalable processors (Sapphire Rapids). 

Wind River Studio provides a cloud-native platform for the development, deployment, operations, and servicing of mission-critical intelligent systems. Its cloud infrastructure capabilities include a fully cloud-native, Kubernetes container-based architecture based on the StarlingX open source project for the deployment and management of distributed edge networks at scale. 

“As 5G opens up new opportunities across industries, there will be an increasing need to put greater intelligence and compute to the edges of the network, where new use cases evolve and thrive. As such, operators must adopt a low-latency far-edge cloud architecture to enable these new use cases in an intelligent, AI-first world,” said Kevin Dallas, president and CEO at Wind River. “Together with Intel, we are providing a best-in-class differentiated solution to help customers deliver on high-reliability, ultra-low-latency, and highly efficient offerings for their next-generation networks.”

http://www.windriver.com/studio

Monday, August 23, 2021

Intel secures foundry contract in Pentagon's RAMP-C program

The U.S. Department of Defense awarded Intel an agreement to provide commercial foundry services in the first phase of its multi-phase Rapid Assured Microelectronics Prototypes - Commercial (RAMP-C) program. 

The RAMP-C program was created to facilitate the use of a U.S.-based commercial semiconductor foundry ecosystem to fabricate the assured leading-edge custom and integrated circuits and commercial products required for critical Department of Defense systems. In October 2020, DOD launched the RAMP program using the Advanced Commercial Capabilities Project Phase 1 Other Transaction Authority. 

The contract was awarded to the newly established Intel Foundry Services business through the NSTXL consortium-based S2MARTS OTA. Financial terms were not disclosed.

“One of the most profound lessons of the past year is the strategic importance of semiconductors, and the value to the United States of having a strong domestic semiconductor industry. Intel is the sole American company both designing and manufacturing logic semiconductors at the leading edge of technology. When we launched Intel Foundry Services earlier this year, we were excited to have the opportunity to make our capabilities available to a wider range of partners, including in the U.S. government, and it is great to see that potential being fulfilled through programs like RAMP-C,” stated Pat Gelsinger, Intel CEO

Under RAMP-C Intel Foundry Services will partner with industry leaders, including IBM, Cadence, Synopsys and others, to support the U.S. government’s needs for designing and manufacturing assured integrated circuits by establishing and demonstrating a semiconductor IP ecosystem to develop and fabricate test chips on Intel 18A, Intel’s most advanced process technology.

“The RAMP-C program will enable both commercial foundry customers and the Department of Defense to take advantage of Intel’s significant investments in leading-edge process technologies,” said Randhir Thakur, Intel Foundry Services president. “Along with our customers and ecosystem partners, including IBM, Cadence, Synopsys and others, we will help bolster the domestic semiconductor supply chain and ensure the United States maintains leadership in both R&D and advanced manufacturing. We look forward to a long-term collaboration with the U.S. government as we deliver RAMP-C program milestones.”

https://www.intel.com/content/www/us/en/newsroom/news/intel-wins-us-project-develop-foundry-ecosystem.html 

U.S. DoD backs Intel for semiconductor packaging tech

The U.S. Department of Defense awarded a contract to Intel to enable the U.S. government to access Intel’s state-of-the-art semiconductor packaging capabilities in Arizona and Oregon.

The project, which is supported by the DoD's State-of-the-Art Heterogeneous Integration Prototype (SHIP) program,  is executed by the Naval Surface Warfare Center, Crane Division, and administered by the National Security Technology Accelerator.

The second phase of SHIP will develop prototypes of multichip packages and accelerate advancement of interface standards, protocols and security for heterogeneous systems. SHIP prototypes will integrate special-purpose government chips with Intel’s advanced, commercially available silicon products, including field programmable gate arrays, application-specific integrated circuits and CPUs. This combination of technologies provides new paths for the U.S. government’s industry partners to develop and modernize the government’s mission-critical systems while taking advantage of Intel’s U.S. manufacturing capabilities.

Heterogeneous packaging allows the assembly of multiple, separately manufactured integrated circuit dies (chips) onto a single package to increase performance while reducing power, size and weight. SHIP provides the U.S. government access to Intel’s advanced heterogeneous packaging technologies, including embedded multi-die interconnect bridge (EMIB), 3D Foveros and Co-EMIB (combining both EMIB and Foveros).

“Intel and the U.S. government share a priority to advance domestic semiconductor manufacturing technology. The SHIP program will enable the Department of Defense to take advantage of Intel’s advanced semiconductor packaging capabilities, diversifying their supply chain and protecting their intellectual property while also supporting ongoing semiconductor R&D in the U.S. and preserving critical capabilities onshore,” stated Jim Brinker, president and general manager of Intel Federal LLC.

“To ensure that the U.S. defense industry base can continue to deliver state-of-the-art electronics for national security, it is imperative that the Department of Defense (DoD) partners with leading U.S. semiconductor companies," Nicole Petta, principal director of microelectronics, Office of the Under Secretary of Defense for Research and Engineering. "The DoD microelectronics roadmap recognizes the importance of strategic partnerships with industry. The roadmap also prioritizes and recognizes that as process scaling slows, heterogeneous assembly technology is a critical investment for both the DoD and our nation. SHIP directly contributes to advancing the objectives outlined in the DoD roadmap and the DoD looks forward to working with Intel, a world leader in this technology.”

http://www.intel.com




In 2018, Intel demonstrated a new 3D packaging technology, called "Foveros," which for the first time brings 3D stacking to logic-on-logic integration. Foveros will will allow products to be broken up into smaller “chiplets,” where I/O, SRAM and power delivery circuits can be fabricated in a base die and high-performance logic chiplets are stacked on top. The first Foveros product will combine a high-performance 10nm compute-stacked chiplet with a low-power 22FFL base die. 

Wednesday, August 11, 2021

Intel appoints Chief People Officer - Christy Pambianchi

Intel announced the appointment of Christy Pambianchi as executive vice president and chief people officer, effective Sept. 7., and reporting to CEO Pat Gelsinger.

Mostly recently, Pambianchi was executive vice president and chief human resources officer at Verizon. She was formerly executive vice president of People & Digital at Corning Inc., where she served in various senior leadership roles during a 20-year tenure. Prior to Corning, Pambianchi was a director of human resources at PepsiCo Inc.


Monday, July 26, 2021

Intel unveils RibbonFET transistor architecture

Intel unveiled RibbonFET, its first new transistor architecture in more than a decade, and PowerVia, a new backside power delivery method. 

In a webcast presentation highlighting its process and packaging technology roadmaps through 2025, Intel vowed a swift adoption of next-generation extreme ultraviolet lithography (EUV), referred to as High Numerical Aperture (High NA) EUV. The company said it is on-track to received the first High NA EUV production tool in the industry.

Intel's roadmap, with new node names, includes:

  • Intel 7 delivers an approximately 10% to 15% performance-per-watt increase versus Intel 10nm SuperFin, based on FinFET transistor optimizations. Intel 7 will be featured in products such as Alder Lake for client in 2021 and Sapphire Rapids for the data center, which is expected to be in production in the first quarter of 2022.
  • Intel 4 fully embraces EUV lithography to print incredibly small features using ultra-short wavelength light. With an approximately 20% performance-per-watt increase, along with area improvements, Intel 4 will be ready for production in the second half of 2022 for products shipping in 2023, including Meteor Lake for client and Granite Rapids for the data center.
  • Intel 3 leverages further FinFET optimizations and increased EUV to deliver an approximately 18% performance-per-watt increase over Intel 4, along with additional area improvements. Intel 3 will be ready to begin manufacturing products in the second half of 2023.
  • Intel 20A ushers in the angstrom era with two breakthrough technologies, RibbonFET and PowerVia. RibbonFET, Intel’s implementation of a gate-all-around transistor, will be the company’s first new transistor architecture since it pioneered FinFET in 2011. The technology delivers faster transistor switching speeds while achieving the same drive current as multiple fins in a smaller footprint. PowerVia is Intel’s unique industry-first implementation of backside power delivery, optimizing signal transmission by eliminating the need for power routing on the front side of the wafer. Intel 20A is expected to ramp in 2024. The company is also excited about the opportunity to partner with Qualcomm using its Intel 20A process technology.
  • 2025 and Beyond: Beyond Intel 20A, Intel 18A is already in development for early 2025 with refinements to RibbonFET that will deliver another major jump in transistor performance. Intel is also working to define, build and deploy next-generation High NA EUV, and expects to receive the first production tool in the industry. Intel is partnering closely with ASML to assure the success of this industry breakthrough beyond the current generation of EUV.

“Intel has a long history of foundational process innovations that have propelled the industry forward by leaps and bounds,” said Dr. Ann Kelleher, senior vice president and general manager of Technology Development. “We led the transition to strained silicon at 90nm, to high-k metal gates at 45nm and to FinFET at 22nm. Intel 20A will be another watershed moment in process technology with two groundbreaking innovations: RibbonFET and PowerVia.”

Regarding its packaging innovations, Intel provided the following updates:

  • Sapphire Rapids will be the first Intel Xeon data center product to ship in volume with EMIB (embedded multi-die interconnect bridge). It will also be the first dual-reticle-sized device in the industry, delivering nearly the same performance as a monolithic design. Beyond Sapphire Rapids, the next generation of EMIB will move from a 55-micron bump pitch to 45 microns.
  • Foveros leverages wafer-level packaging capabilities to provide a first-of-its-kind 3D stacking solution. Meteor Lake will be the second-generation implementation of Foveros in a client product and features a bump pitch of 36 microns, tiles spanning multiple technology nodes and a thermal design power range from 5 to 125W.
  • Foveros Omni ushers in the next generation of Foveros technology by providing unbounded flexibility with performance 3D stacking technology for die-to-die interconnect and modular designs. Foveros Omni allows die disaggregation, mixing multiple top die tiles with multiple base tiles across mixed fab nodes and is expected to be ready for volume manufacturing in 2023.
  • Foveros Direct moves to direct copper-to-copper bonding for low-resistance interconnects and blurs the boundary between where the wafer ends and where the package begins. Foveros Direct enables sub-10-micron bump pitches, providing an order of magnitude increase in the interconnect density for 3D stacking, opening new concepts for functional die partitioning that were previously unachievable. Foveros Direct is complementary to Foveros Omni and is also expected to be ready in 2023.

https://www.intc.com/news-events/press-releases/detail/1486/intel-accelerates-process-and-packaging-innovations


Sunday, July 25, 2021

Intel's Q2 PC sales rise, but data center continues to dip

 Citing record Q2 revenue in its PC and Mobileye businesses, on July 2, Intel reported Q2 revenue of $19.6 billion, flat year over year (YoY), and non-GAAP revenue of $18.5 billion, up 2% YoY, which exceeded April guidance by $700 million. EPS) was $1.24. The results exceeded Q2 guidance for revenue, EPS, and gross margin.

“There’s never been a more exciting time to be in the semiconductor industry. The digitization of everything continues to accelerate, creating a vast growth opportunity for us and our customers across core and emerging business areas. With our scale and renewed focus on both innovation and execution, we are uniquely positioned to capitalize on this opportunity, which I believe is merely the beginning of what will be a decade of sustained growth across the industry,” said Pat Gelsinger, Intel CEO. “Our second-quarter results show that our momentum is building, our execution is improving, and customers continue to choose us for leadership products.”

Gelsinger also stated "While I expect the shortages to bottom out in the second half, it will take another 1 to 2 years before the industry is able to completely catch up with demand. IDM 2.0, which combines our internal manufacturing capacity with the use of third-party foundries, best positions us to weather these challenges and work with our ecosystem partners to build a more resilient supply chain."


Monday, July 19, 2021

Intel elects Andrea Goldsmith to Board of Directors

Andrea Goldsmith, dean of engineering and applied science and professor of electrical and computer engineering at Princeton University, has been elected to Intel’s board of directors.

Dr. Goldsmith spent more than two decades at Stanford University before she was named dean of engineering and applied science at Princeton in 2020. From 2010 to 2014, Goldsmith co-founded and served as the chief technology officer at Plume WiFi (formerly Accelera Inc.), a provider of software-defined wireless networking technology. From 2005 to 2009, Goldsmith also co-founded and served as chief technology officer at Quantenna Communications. Her research focuses on the fundamental performance limits of wireless systems, especially with regard to 5G wireless, the mobile Internet of Things, smart grid design and the applications of communications and signal processing to biology and neuroscience.

Goldsmith has significant public company board experience. She currently serves on the boards of Medtronic and Crown Castle International. Goldsmith has served on the technical advisory boards of several private companies.

Tuesday, June 22, 2021

Intel splits Data Platform Group, Rivera promoted, McKeown joins, Shenoy departs

Intel announced a restructuring of its Data Platform Group (DPG) into two new business units.

  • Sandra Rivera will take on a new role as executive vice president and general manager of Datacenter and AI. Rivera will lead this organization’s focus on developing leadership data center products for a cloud-based world, including Intel Xeon and field programmable gate array (FPGA) products. She will also drive the company’s overall artificial intelligence (AI) strategy. Rivera has a deep history in data center technology and a track record of integrating Intel’s silicon and software portfolios to drive customer value. Prior to her role serving as Intel’s chief people officer, she led Intel’s Network Platforms Group. 
  • Nick McKeown will join Intel full-time on July 6 as senior vice president and general manager of a new Network and Edge Group. This brings Intel’s Network Platforms Group, Internet of Things Group and Connectivity Group into a single business unit chartered to drive technology and product leadership throughout the network to the intelligent edge. Renown in the networking technology industry and recipient of the 2021 IEEE Alexander Graham Bell Medal, McKeown was previously a part-time Intel Senior Fellow who joined the company with its 2019 acquisition of Barefoot Networks, which he co-founded. 

Intel will also create two new business units, one focused on software and one on high performance computing (HPC) and graphics. 

  • Greg Lavender has joined Intel as chief technology officer (CTO) and senior vice president and general manager of the new Software and Advanced Technology Group. This group will drive Intel’s unified vision for software, ensuring it remains a powerful competitive differentiator for the company. As CTO, Lavender will also be responsible for driving Intel’s technical innovation and research programs, including Intel Labs. He brings more than 35 years of experience in software and hardware product engineering and advanced research and development to Intel, most recently serving as senior vice president and CTO of VMware. He has also held key leadership roles at Citigroup, Cisco and Sun Microsystems. 
  • Raja Koduri, a well-known innovator in GPU computing technology, will lead the Accelerated Computing Systems and Graphics Group, a newly formed business unit that will increase the company’s focus in the key growth areas of high performance computing and graphics. AXG is chartered with delivering HPC and graphics solutions for integrated and discrete segments across client, enterprise and data center. Koduri previously served as Intel’s general manager of Architecture, Graphics and Software. 

Rivera, McKeown, Lavender and Koduri will report directly to Pat Gelsinger. Navin Shenoy, who has been serving as executive vice president and general manager of the Data Platforms Group, will assist with the transition and leave Intel on July 6.

Monday, June 21, 2021

Intel cites continued momentum in 5G vRAN and edge

In a virtual event ahead of Mobile World Congress, Intel showcased a number of foundational technologies and products that position the company for continued leadership in 5G virtual radio access network (vRAN) and edge deployments. This includes the following product announcements:

  • Intel Agilex FPGA family is expanding, with a new FPGA with integrated cryptography acceleration that can support MACSec in 5G applications. This adds another layer of security to vRAN at the fronthaul, midhaul and backhaul levels.
  • Intel Ethernet 800 Series family is expanding, with Intel’s first SyncE capable Ethernet Adapter that is designed for space-constrained systems on the edge, and well-suited for both high-bandwidth 4G and 5G RAN as well as other time- and latency-sensitive applications in sectors such as industrial, financial and energy.

In addition, Intel Smart Edge, which consists of two software offerings for the multi-access edge computing layer, will now have a unified architecture and codebase to help customers onboard and manage edge applications and network functions.  Intel Smart Edge is commercial software focused on enterprise on-premise use cases, such as private networks and universal Customer Premise equipment. The evolved and enhanced Intel Smart Edge Open (formerly known as OpenNESS) is an open software toolkit that enables developers to build highly optimized and performant edge platforms.



The virtual event also highlighted key partnerships for Intel, including:

  • Reliance Jio announced it will do co-innovations with Intel in 5G radio and wireless core, and collaborate in other associate areas that include AI, cloud and edge computing, which will help it as they deploy 5G.
  • Deutsche Telekom is using Intel FlexRAN technology with accelerators in O-RAN Town, in the O-RAN network it is deploying in Neubrandenburg, Germany — a city of 65,000 people spread out over 33 square miles. The company is relying on Intel as a technology partner as it delivers high-performance RAN at scale.
  • DISH Wireless relies on Intel’s contributions to the 5G ecosystem as it builds out the first cloud-native 5G network in the United States. The launch in its first city, Las Vegas, as well as its nationwide network, will be deployed on infrastructure powered by Intel technology in the network core, access and edge.
  • Cohere is pioneering a new approach to improve spectrum utilization by leveraging capabilities in FlexRAN. It is integrating and optimizing spectrum multiplier software in the RAN intelligent controller. Cohere’s testing shows its Delay Doppler spatial multiplexing technology is improving channel estimation and delivering up to a two-times improvement in spectrum utilization for operators. That’s what Vodafone has seen in 700Mhz testing in its labs.

“Network transformation is critical to unleash the possibilities of 5G and maximize the rise of the edge to create new and better business outcomes for our customers across the globe. As the leading network silicon provider, we have been driving this shift to virtualizing the core to access to edge, and implementing edge computing capabilities with our decade of experience, to power our society’s digital revolution”, said Dan Rodriguez, Intel corporate vice president, Network Platforms Group.

Thursday, June 17, 2021

Intel rolls FPGA-based Infrastructure Processing Unit (IPU)

Intel outlined its vision for the infrastructure processing unit (IPU), a programmable network device that intelligently manages system-level infrastructure resources by securely accelerating those functions in a data center.

In a video, Guido Appenzeller, chief technology officer with Intel's Data Platforms Group says the idea is to cleanly separate the processing of client workloads from workloads of the cloud service provider.

Intel cites several advantages for an IPU architecture. First, cloud service providers will be able to process their workloads very efficiently on silicon designed for the tasks. The cloud service provider will be able to rent out 100% of available CPU resources to the clients. The clients are now able to fully control the CPUs including with their own hypervisors. In addition, local disk storage can be enhanced or replaced with virtual storage connected to the network. 

The first instances of Intel's FPGA-based IPU platforms are already shipping. Intel will be rolling out additional FPGA-based IPUs and integrated ASICs as well. "As a result of Intel’s collaboration with a majority of hyperscalers, Intel is already the volume leader in the IPU market with our Xeon-D, FPGA and Ethernet components,” said Patty Kummrow, vice president in the Data Platforms Group and general manager of Ethernet Products Group at Intel. “The first of Intel’s FPGA-based IPU platforms are deployed at multiple cloud service providers and our first ASIC IPU is under test.”

https://youtu.be/ahChxDyl8t4

https://www.intel.com/content/www/us/en/newsroom/news/infrastructure-processing-unit-data-center.html





Tuesday, May 18, 2021

Intel's Mobileye wins ADAS design contract with Toyota

Toyota Motor Corp. selected Intel and ZF to develop advanced driver-assistance systems (ADAS) for use in multiple vehicle platforms starting in the next few years. 

As part of the agreement, ZF, one of the world’s largest producers of automotive cameras driven by Mobileye technology, will also supply its Gen 21 mid-range radar and be responsible for the integration of camera and radar in Toyota vehicles.

ZF and Mobileye will collaborate closely to produce advanced camera technology integrated with ZF radar technology to power key advanced driver-assistance platforms in Toyota vehicles. 

ZF’s Gen21 mid-range radar is a high-performance 77 GHz front radar designed to meet 2022+ Euro NCAP 5-Star Safety Ratings and enable L2/L2+ Automated Driving functions.

Monday, May 3, 2021

Intel to upgrade its New Mexico fab for 3D semiconductor packaging

Intel announced plans to $3.5 billion to equip its New Mexico operations for the manufacturing of advanced semiconductor packaging technologies, including Foveros, its 3D packaging technology.

Foveros advanced 3D packaging technology enables Intel to build processors with compute tiles stacked vertically, rather than side-by-side, providing greater performance in a smaller footprint. It also allows Intel to mix and match compute tiles to optimize for cost and power efficiency. 

“A key differentiator for our IDM 2.0 strategy is our unquestioned leadership in advanced packaging, which allows us to mix and match compute tiles to deliver the best products. We’re seeing tremendous interest in these capabilities from the industry, especially following the introduction of our new Intel Foundry Services. We’re proud to have invested in New Mexico for more than 40 years and we see our Rio Rancho campus continuing to play a critical role in Intel’s global manufacturing network in our new era of IDM 2.0," stated Keyvan Esfarjani, Intel senior vice president and general manager of Manufacturing and Operations.

  • In 2018, Intel first demonstrated a new 3D packaging technology, called "Foveros," which for the first time brings 3D stacking to logic-on-logic integration. Foveros will allow products to be broken up into smaller “chiplets,” where I/O, SRAM and power delivery circuits can be fabricated in a base die and high-performance logic chiplets are stacked on top. 
























U.S. DoD backs Intel for semiconductor packaging tech

The U.S. Department of Defense awarded a contract to Intel to enable the U.S. government to access Intel’s state-of-the-art semiconductor packaging capabilities in Arizona and Oregon.The project, which is supported by the DoD's State-of-the-Art Heterogeneous Integration Prototype (SHIP) program,  is executed by the Naval Surface Warfare Center, Crane Division, and administered by the National Security Technology Accelerator.The second phase...





Thursday, April 22, 2021

Intel posts rise in EPS, dip in data center sales

 Intel reported Q1 revenue of $19.7 billion (GAAP), down 1 percent year over year (YoY), and non-GAAP revenue of $18.6 billion, flat YoY, which exceeded January guidance by $1.1 billion. First-quarter GAAP earnings-per-share (EPS) was $0.82; non-GAAP EPS was $1.39, which exceeded January guidance by $0.29.

“Intel delivered strong first-quarter results driven by exceptional demand for our leadership products and outstanding execution by our team. The response to our new IDM 2.0 strategy has been extraordinary, our product roadmap is gaining momentum, and we’re rapidly progressing our plans with re-invigorated focus on innovation and execution,” said Pat Gelsinger, Intel CEO. “This is a pivotal year for Intel. We are setting our strategic foundation and investing to accelerate our trajectory and capitalize on the explosive growth in semiconductors that power our increasingly digital world.”

First-quarter revenue exceeded January guidance by $1.1 billion led by continued, 

Intel said its results were driven by strong PC demand. PC unit volumes were up 38 percent YoY, and notebook volumes set a new Intel record. The company also saw initial recovery of Enterprise and Government sales in the Data Center Group (DCG). 

Intel also achieved better-than-expected revenue in Internet of Things Group (IOTG) and Mobileye, and Mobileye set a new revenue record in the quarter.



https://www.intc.com/financial-info

Tuesday, April 6, 2021

Intel intros 3rd Gen Xeon including four NFV optimized versions

Intel launched its 3rd Gen Xeon Scalable processors (code-named “Ice Lake”) featuring an average 46% improvement on popular data center workloads over the previous generation.

The new Xeon processors, which are the foundation of Intel’s data center platform, also add new and enhanced platform capabilities including Intel SGX for built-in security, and Intel Crypto Acceleration and Intel DL Boost for AI acceleration. 

The processors use Intel 10 nanometer (nm) process technology and deliver up to 40 cores per processor and up to 2.65 times higher average performance gain compared with a 5-year-old system. The platform supports up to 6 terabytes of system memory per socket, up to 8 channels of DDR4-3200 memory per socket and up to 64 lanes of PCIe Gen4 per socket.

Intel is also offering network-optimized “N-SKUs” that are designed for diverse network environments for vRAN, NFVI, virtual CDN and more.

“Our 3rd Gen Intel Xeon Scalable platform is the most flexible and performant in our history, designed to handle the diversity of workloads from the cloud to the network to the edge,” said Navin Shenoy, executive vice president and general manager of the Data Platforms Group at Intel. “Intel is uniquely positioned with the architecture, design and manufacturing to deliver the breadth of intelligent silicon and solutions our customers demand.”


https://www.intc.com/news-events/press-releases/detail/1457/intel-launches-its-most-advanced-performance-data-center

Tuesday, March 23, 2021

Intel sets course with new integrated device manufacturing strategy

Intel CEO Pat Gelsinger outlined the company’s path forward to an integrated device manufacturing model. The IDM2 strategy has 3 elements:

Building Intel’s global, internal factory network for at-scale manufacturing. Intel said its 7nm development is progressing well, driven by increased use of extreme ultraviolet lithography (EUV) in a rearchitected, simplified process flow. Intel expects to tape in the compute tile for its first 7nm client CPU  in the second quarter of this year.

Expanding the use of third-party foundry capacity to include the manufacturing for a range of modular tiles on advanced process technologies, including products at the core of Intel’s computing offerings for both client and data center segments beginning in 2023. 

Creating a new Intel Foundry Services with plans to become a major provider of U.S.– and Europe-based foundry capacity to serve the incredible global demand for semiconductor manufacturing. The new business will be headed by Dr. Randhir Thakur.  IFS will be differentiated from other foundry offerings with a combination of leading-edge process technology and packaging, committed capacity in the U.S. and Europe, and a world-class IP portfolio for customers, including x86 cores as well as ARM and RISC-V ecosystem IPs.

During the company’s global “Intel Unleashed: Engineering the Future” webcast, Intel CEO Pat Gelsinger announced a $20 billion investment to build two new fabs in Arizona, located at the company’s Ocotillo campus. 

“We are setting a course for a new era of innovation and product leadership at Intel,” said Gelsinger. “Intel is the only company with the depth and breadth of software, silicon and platforms, packaging, and process with at-scale manufacturing customers can depend on for their next-generation innovations. IDM 2.0 is an elegant strategy that only Intel can deliver – and it’s a winning formula. We will use it to design the best products and manufacture them in the best way possible for every category we compete in.” 

In addition, Intel and IBM announced plans for an important research collaboration focused on creating next–generation logic and packaging technologies.

https://newsroom.intel.com/news-releases/idm-manufacturing-innovation-product-leadership/#gs.wf9f4f

Sunday, March 21, 2021

DARPA seeks to boost domestic manufacturing of structured ASICs

The U.S. Defense Advanced Research Projects Agency (DARPA) is launching an industry collaboration with Intel to expand access to domestic manufacturing capabilities for custom chips for defense systems. 

DARPA's Structured Array Hardware for Automatically Realized Applications (SAHARA) program is partnership with Intel and academic researchers from University of Florida, University of Maryland, and Texas A&M to develop U.S.-based manufacturing capabilities to enable the automated and scalable conversion of defense-relevant field-programmable gate array (FPGAs) designs into quantifiably secure Structured ASICs. 

SAHARA will also explore novel chip protections to support the manufacturing of silicon in zero-trust environments. While FPGAs are widely used in military applications today, Structured ASICs deliver significantly higher performance and lower power consumption.

For its part, Intel said it will use its structured ASIC technology to develop platforms that significantly accelerate development time and reduce engineering cost compared to traditional ASICs. 

Intel plans to manufacture these chips using its 10nm process technology with the advanced interface bus die-to-die interconnect and embedded multi-die interconnect bridge packaging technology to integrate multiple heterogenous die in a single package.

Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs. 

"We are combining our most advanced Intel eASIC structured ASIC technology with state-of-the-art data interface chiplets and enhanced security protection, and it’s all being made within the U.S. from beginning to end. This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10nm semiconductor process," stated José Roberto Alvarez, senior director, CTO Office, Intel Programmable Solutions Group.

SAHARA is a critical program supporting the Department of Defense (DoD) microelectronics Roadmap led by the Under Secretary of Defense for Research and Engineering – USD(R&E) – to define, quantify, and standardize security while strengthening domestic semiconductor manufacturing. The Rapid Assured Microelectronics Prototypes-Commercial (RAMP-C) and State-of-the-Art Heterogeneous Integration Prototype (SHIP) projects are also integral to the DoD Roadmap.

“The structured ASIC platforms and methods developed in SAHARA together with the advanced packaging technology developed in SHIP will enable the U.S. Department of Defense to more quickly and cost effectively develop and deploy advanced microelectronic systems critical to DoD modernization priorities,” said Brett Hamilton, deputy principal director for Microelectronics in USD(R&E).

https://www.darpa.mil/news-events/2021-03-18

Lattice Semiconductor joins DARPA Toolbox Initiative

Lattice Semiconductor's Diamond and FPGA design tools for its highly reliable, low-power, small form factor FPGAs are now included in the DARPA Toolbox initiative. The DARPA Toolbox initiative is a new, agency-wide effort aimed at providing access to state-of-the-art technology from leading commercial technology vendors to the researchers behind DARPA programs.The partnership also provides DARPA organizations with access to a selection of Lattice's...

DARPA launches Data Protection in Virtual Environments

The U.S. Defense Advanced Research Projects Agency (DARPA) launched an initiative called the Data Protection in Virtual Environments (DPRIVE) program which seeks to develop a hardware accelerator for Fully Homomorphic Encryption (FHE).Fully homomorphic encryption enables users to compute on always-encrypted data, or cryptograms. The data never needs to be decrypted, reducing the potential for cyberthreats.DPRIVE aims to design and implement a hardware...

The Defense Advanced Research Projects Agency (DARPA) reached an agreement with The Linux Foundation to create open source software that accelerates United States government technology research and development innovation.Specifically, DARPA and the LF will create a broad collaboration umbrella (US Government Open Programmable Secure (US GOV OPS) that allows United States Government projects, their ecosystem, and open community to participate in accelerating...

ONF's Aether Edge Cloud selected for DARPA's Pronto Project

The Open Networking Foundation's Aether 5G Connected Edge Cloud platform is being used as the software platform for Pronto, a project backed by $30 million in DARPA funding to develop secure 5G network infrastructure. Specifically, DARPA is funding ONF to build, deploy and operate the network to support research by Cornell, Princeton and Stanford universities in the areas of network verification and closed-loop control. Aether (pronounced ‘ee-ther’)...

DARPA backs Lasers for Universal Microscale Optical Systems program

DARPA is backing a new Lasers for Universal Microscale Optical Systems (LUMOS) program, which aims to bring high-performance lasers to advanced photonics platforms. Three LUMOS Technical Areas are cited:bringing high-performance lasers and optical amplifiers into advanced domestic photonics manufacturing foundries. Tower Semiconductor and SUNY Polytechnic Institute were selected to demonstrate flexible, efficient on-chip optical gain in their...


Monday, March 8, 2021

DARPA launches Data Protection in Virtual Environments

The U.S. Defense Advanced Research Projects Agency (DARPA) launched an initiative called the Data Protection in Virtual Environments (DPRIVE) program which seeks to develop a hardware accelerator for Fully Homomorphic Encryption (FHE).

Fully homomorphic encryption enables users to compute on always-encrypted data, or cryptograms. The data never needs to be decrypted, reducing the potential for cyberthreats.

DPRIVE aims to design and implement a hardware accelerator for FHE computations that is capable of drastically speeding up FHE calculations, making the technology more accessible for sensitive defense applications as well as commercial use.

DARPA has selected four teams of researchers to lead the initiative: Duality Technologies, Galois, SRI International, and Intel Federal. Each team will develop an FHE accelerator hardware and software stack that reduces the computational overhead required to make FHE calculations to a speed comparable to similar unencrypted data operations. The teams will create accelerator architectures that are flexible, scalable, and programmable, but will also explore various approaches with different native word sizes. Current standard CPUs are based on 64-bit words, which are the units of data that determine a particular processor’s design. Word size directly relates to the signal-to-noise ratio of how encrypted data is stored and processed, as well as the error generated each time an FHE calculation is processed. The selected DPRIVE research teams will explore various approaches covering a diversity of word sizes – from 64 bits to thousands of bits – to solve the challenge.

In addition, teams are exploring novel approaches to memory management, flexible data structures and programming models, and formal verification methods to ensure the FHE implementation is correct-by-design and provides confidence to the user. As the co-design of FHE algorithms, hardware, and software is critical to the successful creation of the target DPRIVE accelerator, each team is bringing varied technical expertise to the program as well as in-depth knowledge on FHE.

“We currently estimate we are about a million times slower to compute in the FHE world then we are in the plaintext world. The goal of DPRIVE is to bring FHE down to the computational speeds we see in plaintext. If we are able to achieve this goal while positioning the technology to scale, DPRIVE will have a significant impact on our ability to protect and preserve data and user privacy,” concluded Rondeau.

“Fully homomorphic encryption remains the holy grail in the quest to keep data secure while in use. Despite strong advances in trusted execution environments and other confidential computing technologies to protect data while at rest and in transit, data is unencrypted during computation, opening the possibility of potential attacks at this stage. This frequently inhibits our ability to fully share and extract the maximum value out of data. We are pleased to be chosen as a technology partner by DARPA and look forward to working with them as well as Microsoft to advance this next chapter in confidential computing and unlock the promise of fully homomorphic encryption for all,” stated Rosario Cammarota, principal engineer, Intel Labs, and principal investigator, DARPA DPRIVE program.

For its part, Intel says it plans to design an application-specific integrated circuit (ASIC) accelerator to reduce the performance overhead currently associated with fully homomorphic encryption. When fully realized, the accelerator could deliver a massive improvement in executing FHE workloads over existing CPU-driven systems, potentially reducing cryptograms’ processing time by five orders of magnitude.

With its expertise in cloud infrastructure, software stacks and fully homomorphic encryption, Microsoft will be a critical partner in accelerating the commercialization of this technology when ready, enabling free data sharing and collaboration while promoting privacy throughout the data life cycle.

“We are pleased to bring our expertise in cloud computing and homomorphic encryption to the DARPA DPRIVE program, collaborating with Intel to advance this transformative technology when ready into commercial usages that will help our customers close the last-mile gap in data confidentiality —– keeping data fully secure and private, whether in storage, transit or use,” said Dr. William Chappell, chief technology officer, Azure Global, and vice president, Mission Systems, Microsoft.