Showing posts with label Intel. Show all posts
Showing posts with label Intel. Show all posts

Tuesday, April 6, 2021

Intel intros 3rd Gen Xeon including four NFV optimized versions

Intel launched its 3rd Gen Xeon Scalable processors (code-named “Ice Lake”) featuring an average 46% improvement on popular data center workloads over the previous generation.

The new Xeon processors, which are the foundation of Intel’s data center platform, also add new and enhanced platform capabilities including Intel SGX for built-in security, and Intel Crypto Acceleration and Intel DL Boost for AI acceleration. 

The processors use Intel 10 nanometer (nm) process technology and deliver up to 40 cores per processor and up to 2.65 times higher average performance gain compared with a 5-year-old system. The platform supports up to 6 terabytes of system memory per socket, up to 8 channels of DDR4-3200 memory per socket and up to 64 lanes of PCIe Gen4 per socket.

Intel is also offering network-optimized “N-SKUs” that are designed for diverse network environments for vRAN, NFVI, virtual CDN and more.

“Our 3rd Gen Intel Xeon Scalable platform is the most flexible and performant in our history, designed to handle the diversity of workloads from the cloud to the network to the edge,” said Navin Shenoy, executive vice president and general manager of the Data Platforms Group at Intel. “Intel is uniquely positioned with the architecture, design and manufacturing to deliver the breadth of intelligent silicon and solutions our customers demand.”


https://www.intc.com/news-events/press-releases/detail/1457/intel-launches-its-most-advanced-performance-data-center

Tuesday, March 23, 2021

Intel sets course with new integrated device manufacturing strategy

Intel CEO Pat Gelsinger outlined the company’s path forward to an integrated device manufacturing model. The IDM2 strategy has 3 elements:

Building Intel’s global, internal factory network for at-scale manufacturing. Intel said its 7nm development is progressing well, driven by increased use of extreme ultraviolet lithography (EUV) in a rearchitected, simplified process flow. Intel expects to tape in the compute tile for its first 7nm client CPU  in the second quarter of this year.

Expanding the use of third-party foundry capacity to include the manufacturing for a range of modular tiles on advanced process technologies, including products at the core of Intel’s computing offerings for both client and data center segments beginning in 2023. 

Creating a new Intel Foundry Services with plans to become a major provider of U.S.– and Europe-based foundry capacity to serve the incredible global demand for semiconductor manufacturing. The new business will be headed by Dr. Randhir Thakur.  IFS will be differentiated from other foundry offerings with a combination of leading-edge process technology and packaging, committed capacity in the U.S. and Europe, and a world-class IP portfolio for customers, including x86 cores as well as ARM and RISC-V ecosystem IPs.

During the company’s global “Intel Unleashed: Engineering the Future” webcast, Intel CEO Pat Gelsinger announced a $20 billion investment to build two new fabs in Arizona, located at the company’s Ocotillo campus. 

“We are setting a course for a new era of innovation and product leadership at Intel,” said Gelsinger. “Intel is the only company with the depth and breadth of software, silicon and platforms, packaging, and process with at-scale manufacturing customers can depend on for their next-generation innovations. IDM 2.0 is an elegant strategy that only Intel can deliver – and it’s a winning formula. We will use it to design the best products and manufacture them in the best way possible for every category we compete in.” 

In addition, Intel and IBM announced plans for an important research collaboration focused on creating next–generation logic and packaging technologies.

https://newsroom.intel.com/news-releases/idm-manufacturing-innovation-product-leadership/#gs.wf9f4f

Sunday, March 21, 2021

DARPA seeks to boost domestic manufacturing of structured ASICs

The U.S. Defense Advanced Research Projects Agency (DARPA) is launching an industry collaboration with Intel to expand access to domestic manufacturing capabilities for custom chips for defense systems. 

DARPA's Structured Array Hardware for Automatically Realized Applications (SAHARA) program is partnership with Intel and academic researchers from University of Florida, University of Maryland, and Texas A&M to develop U.S.-based manufacturing capabilities to enable the automated and scalable conversion of defense-relevant field-programmable gate array (FPGAs) designs into quantifiably secure Structured ASICs. 

SAHARA will also explore novel chip protections to support the manufacturing of silicon in zero-trust environments. While FPGAs are widely used in military applications today, Structured ASICs deliver significantly higher performance and lower power consumption.

For its part, Intel said it will use its structured ASIC technology to develop platforms that significantly accelerate development time and reduce engineering cost compared to traditional ASICs. 

Intel plans to manufacture these chips using its 10nm process technology with the advanced interface bus die-to-die interconnect and embedded multi-die interconnect bridge packaging technology to integrate multiple heterogenous die in a single package.

Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs. 

"We are combining our most advanced Intel eASIC structured ASIC technology with state-of-the-art data interface chiplets and enhanced security protection, and it’s all being made within the U.S. from beginning to end. This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10nm semiconductor process," stated José Roberto Alvarez, senior director, CTO Office, Intel Programmable Solutions Group.

SAHARA is a critical program supporting the Department of Defense (DoD) microelectronics Roadmap led by the Under Secretary of Defense for Research and Engineering – USD(R&E) – to define, quantify, and standardize security while strengthening domestic semiconductor manufacturing. The Rapid Assured Microelectronics Prototypes-Commercial (RAMP-C) and State-of-the-Art Heterogeneous Integration Prototype (SHIP) projects are also integral to the DoD Roadmap.

“The structured ASIC platforms and methods developed in SAHARA together with the advanced packaging technology developed in SHIP will enable the U.S. Department of Defense to more quickly and cost effectively develop and deploy advanced microelectronic systems critical to DoD modernization priorities,” said Brett Hamilton, deputy principal director for Microelectronics in USD(R&E).

https://www.darpa.mil/news-events/2021-03-18

Lattice Semiconductor joins DARPA Toolbox Initiative

Lattice Semiconductor's Diamond and FPGA design tools for its highly reliable, low-power, small form factor FPGAs are now included in the DARPA Toolbox initiative. The DARPA Toolbox initiative is a new, agency-wide effort aimed at providing access to state-of-the-art technology from leading commercial technology vendors to the researchers behind DARPA programs.The partnership also provides DARPA organizations with access to a selection of Lattice's...

DARPA launches Data Protection in Virtual Environments

The U.S. Defense Advanced Research Projects Agency (DARPA) launched an initiative called the Data Protection in Virtual Environments (DPRIVE) program which seeks to develop a hardware accelerator for Fully Homomorphic Encryption (FHE).Fully homomorphic encryption enables users to compute on always-encrypted data, or cryptograms. The data never needs to be decrypted, reducing the potential for cyberthreats.DPRIVE aims to design and implement a hardware...

The Defense Advanced Research Projects Agency (DARPA) reached an agreement with The Linux Foundation to create open source software that accelerates United States government technology research and development innovation.Specifically, DARPA and the LF will create a broad collaboration umbrella (US Government Open Programmable Secure (US GOV OPS) that allows United States Government projects, their ecosystem, and open community to participate in accelerating...

ONF's Aether Edge Cloud selected for DARPA's Pronto Project

The Open Networking Foundation's Aether 5G Connected Edge Cloud platform is being used as the software platform for Pronto, a project backed by $30 million in DARPA funding to develop secure 5G network infrastructure. Specifically, DARPA is funding ONF to build, deploy and operate the network to support research by Cornell, Princeton and Stanford universities in the areas of network verification and closed-loop control. Aether (pronounced ‘ee-ther’)...

DARPA backs Lasers for Universal Microscale Optical Systems program

DARPA is backing a new Lasers for Universal Microscale Optical Systems (LUMOS) program, which aims to bring high-performance lasers to advanced photonics platforms. Three LUMOS Technical Areas are cited:bringing high-performance lasers and optical amplifiers into advanced domestic photonics manufacturing foundries. Tower Semiconductor and SUNY Polytechnic Institute were selected to demonstrate flexible, efficient on-chip optical gain in their...


Monday, March 8, 2021

DARPA launches Data Protection in Virtual Environments

The U.S. Defense Advanced Research Projects Agency (DARPA) launched an initiative called the Data Protection in Virtual Environments (DPRIVE) program which seeks to develop a hardware accelerator for Fully Homomorphic Encryption (FHE).

Fully homomorphic encryption enables users to compute on always-encrypted data, or cryptograms. The data never needs to be decrypted, reducing the potential for cyberthreats.

DPRIVE aims to design and implement a hardware accelerator for FHE computations that is capable of drastically speeding up FHE calculations, making the technology more accessible for sensitive defense applications as well as commercial use.

DARPA has selected four teams of researchers to lead the initiative: Duality Technologies, Galois, SRI International, and Intel Federal. Each team will develop an FHE accelerator hardware and software stack that reduces the computational overhead required to make FHE calculations to a speed comparable to similar unencrypted data operations. The teams will create accelerator architectures that are flexible, scalable, and programmable, but will also explore various approaches with different native word sizes. Current standard CPUs are based on 64-bit words, which are the units of data that determine a particular processor’s design. Word size directly relates to the signal-to-noise ratio of how encrypted data is stored and processed, as well as the error generated each time an FHE calculation is processed. The selected DPRIVE research teams will explore various approaches covering a diversity of word sizes – from 64 bits to thousands of bits – to solve the challenge.

In addition, teams are exploring novel approaches to memory management, flexible data structures and programming models, and formal verification methods to ensure the FHE implementation is correct-by-design and provides confidence to the user. As the co-design of FHE algorithms, hardware, and software is critical to the successful creation of the target DPRIVE accelerator, each team is bringing varied technical expertise to the program as well as in-depth knowledge on FHE.

“We currently estimate we are about a million times slower to compute in the FHE world then we are in the plaintext world. The goal of DPRIVE is to bring FHE down to the computational speeds we see in plaintext. If we are able to achieve this goal while positioning the technology to scale, DPRIVE will have a significant impact on our ability to protect and preserve data and user privacy,” concluded Rondeau.

“Fully homomorphic encryption remains the holy grail in the quest to keep data secure while in use. Despite strong advances in trusted execution environments and other confidential computing technologies to protect data while at rest and in transit, data is unencrypted during computation, opening the possibility of potential attacks at this stage. This frequently inhibits our ability to fully share and extract the maximum value out of data. We are pleased to be chosen as a technology partner by DARPA and look forward to working with them as well as Microsoft to advance this next chapter in confidential computing and unlock the promise of fully homomorphic encryption for all,” stated Rosario Cammarota, principal engineer, Intel Labs, and principal investigator, DARPA DPRIVE program.

For its part, Intel says it plans to design an application-specific integrated circuit (ASIC) accelerator to reduce the performance overhead currently associated with fully homomorphic encryption. When fully realized, the accelerator could deliver a massive improvement in executing FHE workloads over existing CPU-driven systems, potentially reducing cryptograms’ processing time by five orders of magnitude.

With its expertise in cloud infrastructure, software stacks and fully homomorphic encryption, Microsoft will be a critical partner in accelerating the commercialization of this technology when ready, enabling free data sharing and collaboration while promoting privacy throughout the data life cycle.

“We are pleased to bring our expertise in cloud computing and homomorphic encryption to the DARPA DPRIVE program, collaborating with Intel to advance this transformative technology when ready into commercial usages that will help our customers close the last-mile gap in data confidentiality —– keeping data fully secure and private, whether in storage, transit or use,” said Dr. William Chappell, chief technology officer, Azure Global, and vice president, Mission Systems, Microsoft.


Tuesday, February 23, 2021

Google Cloud and Intel partner on telco cloud architectures

 Google Cloud and Intel agreed to develop telco cloud reference architectures and integrated solutions for communication service providers to accelerate 5G deployment across multiple network and edge locations. 

The partnership is focused on:

  • Accelerating the ability of communications service providers to deploy their virtualized radio access network (RAN) and open RAN solutions with next-generation infrastructure and hardware.
  • Launching new lab environments to help communications service providers innovate for cloud native-based 5G networks.
  • Making it easier for communications service providers to deliver business applications to the network edge.

“Communications service providers can adopt cloud-native technologies to harness the potential of 5G both as a connectivity solution and as a business services platform to deliver applications to the network edge,” said Shailesh Shukla, vice president and general manager of networking at Google Cloud. “Expanding on our work with the telecommunications industry, we are excited to work with Intel to help customers plan, test and deploy the technology and infrastructure needed to accelerate the delivery of cloud-native 5G for consumer and enterprise use cases.”

Intel said the collaboration marks another important step forward in its journey to help transform the 5G network with a software-defined, agile and scalable infrastructure.

“The next wave of network transformation is fueled by 5G and is driving a rapid transition to cloud-native technologies. As communications service providers build out their 5G network infrastructure, our efforts with Google and the broader ecosystem will help them deliver agile, scalable solutions for emerging 5G and edge use cases,” said Dan Rodriguez, corporate vice president and general manager of the Network Platforms Group at Intel.

Google Cloud said it is working closely with Intel in three main areas: accelerating the ability of communications service providers to deploy their Virtualized RAN (vRAN) and Open Radio Access Network (ORAN) solutions by providing next-generation infrastructure and hardware, launching new lab environments to help communications service providers innovate on cloud-native 5G, and making it easier for them to deliver business applications to the network edge. 

Regarding 5G vRAN deployments, the architecture will leverage Google Cloud’s global infrastructure and capabilities alongside Intel’s FlexRAN reference software; Intel’s cloud-native Open Network Edge Service Software (OpenNESS) deployment model and best practices applicable to Anthos; Intel’s Data Plane Development Kit (DPDK) and hardware infrastructure based on Intel Xeon processors; and New reference architecture and solutions to accelerate 5G vRAN with Anthos, an application platform.

In addition, Google Cloud will jointly launch a Network Functions Validation lab and collaborate with Intel to support vendors in testing, optimizing, and validating their core network functions running on Google Cloud’s Anthos for Telecom platform. 

https://newsroom.intel.com/news/intel-google-cloud-aim-advance-5g-networks-edge-innovations/#gs.ubx9fa

https://cloud.google.com/blog/topics/partners/speeding-up-cloud-native-5g-networks-with-intel-and-google-cloud

Google Cloud and Nokia announce Telco Cloud Partnership

Google Cloud and Nokia announced a global, strategic partnership focused on cloud-native solutions for communications service providers (CSPs), including a cloud-native 5G Core and a network edge for business services.Under this partnership, Google Cloud and Nokia will work closely to validate, optimize and evolve cloud-native network functions, and the two companies will also co-innovate new solutions that will help CSPs deliver 5G connectivity...


Wednesday, January 27, 2021

Intel re-hires Sunil Shenoy to lead Design Engineering Group

Intel announced the appointment of Sunil Shenoy as senior vice president and general manager of the Design Engineering Group.

Shenoy, a 33-year Intel veteran who departed in 2014, will lead design, development, validation and manufacturing of intellectual properties and system-on-chips (SOC) for client and data center applications. 

Most recently, Shenoy was senior vice president and general manager of RISC-V at SiFive, an Intel Capital portfolio company working to commercialize the RISC-V open architecture. At SiFive, Shenoy helped build the engineering team. In his prior years at Intel, Shenoy was corporate vice president in charge of Intel’s Platform Engineering Group, responsible for microprocessor and SoC design across Intel’s product groups. He also led Intel’s Visual and Parallel Computing Group and server and PC silicon development R&D and engineering, among other responsibilities.


Thursday, January 21, 2021

Intel posts Q4 revenue of $20 billion, exceeding guidance

Intel reported Q4 2020 revenue of $20.0 billion, exceeding October guidance by $2.6 billion and down 1 percent year-over-year (YoY). Full-year revenue set an all-time Intel record of $77.9 billion, up 8 percent YoY. Earnings per share (EPS) amounted to $1.42 ($1.52 on a non-GAAP basis, exceeding October guidance by 42 cents).

“We significantly exceeded our expectations for the quarter, capping off our fifth consecutive record year,” said Bob Swan, Intel CEO. “Demand for the computing performance Intel delivers remains very strong and our focus on growth opportunities is paying off. It has been an honor to lead this wonderful company, and I am proud of what we have achieved as a team. Intel is in a strong strategic and financial position as we make this leadership transition and take Intel to the next level.”

Q4'20 Business Highlights

  • Started production of 10nm-based 3rd Gen Intel Xeon Scalable processors (“Ice Lake”), ramping in Q1.
  • Launched 11th Gen Intel Core processors ("Tiger Lake"); announced 11th Gen Intel Core™ S-Series desktop processors ("Rocket Lake"), now shipping.
  • Entered discrete graphics market with Intel Iris Xe MAX graphics, Intel’s first Xe-based discrete GPU.
  • Announced Amazon Web Services selected Intel's Habana Gaudi AI processors for EC2 training.
  • Delivered gold release of Intel oneAPI developer toolkit.
  • Announced expanded network infrastructure solutions portfolio.
  • Introduced new Intel Optane SSD series and 3rd gen Intel Optane persistent memory “Crow Pass” for enterprise and cloud customers.


Wednesday, January 13, 2021

Intel appoints Pat Gelsinger as next CEO

Intel's Board of Directors appointed Pat Gelsinger as the company's new chief executive officer, effective Feb. 15, 2021, replacing Bob Swan.

Gelsinger has served as the CEO of VMware since 2012, where he significantly transformed the company into a recognized global leader in cloud infrastructure, enterprise mobility and cyber security, almost tripling the company’s annual revenues. Prior to joining VMware, Gelsinger was president and chief operating officer of EMC Information Infrastructure Products at EMC, overseeing engineering and operations for information storage, data computing, backup and recovery, RSA security and enterprise solutions. Before joining EMC, he spent 30 years at Intel, becoming the company’s first chief technology officer and driving the creation of key industry technologies such as USB and Wi-Fi. He was the architect of the original 80486 processor, led 14 different microprocessor programs and played key roles in the Core and Xeon families.

“Pat is a proven technology leader with a distinguished track record of innovation, talent development, and a deep knowledge of Intel. He will continue a values-based cultural leadership approach with a hyper focus on operational execution,” said Omar Ishrak, independent chairman of the Intel board. “After careful consideration, the board concluded that now is the right time to make this leadership change to draw on Pat’s technology and engineering expertise during this critical period of transformation at Intel. The board is confident that Pat, together with the rest of the leadership team, will ensure strong execution of Intel’s strategy to build on its product leadership and take advantage of the significant opportunities ahead as it continues to transform from a CPU to a multi-architecture XPU company.”

“I am thrilled to rejoin and lead Intel forward at this important time for the company, our industry and our nation,” said Gelsinger. “Having begun my career at Intel and learned at the feet of Grove, Noyce and Moore, it’s my privilege and honor to return in this leadership capacity. I have tremendous regard for the company’s rich history and powerful technologies that have created the world’s digital infrastructure. I believe Intel has significant potential to continue to reshape the future of technology and look forward to working with the incredibly talented global Intel team to accelerate innovation and create value for our customers and shareholders.”

“My goal over the past two years has been to position Intel for a new era of distributed intelligence, improving execution to strengthen our core CPU franchise and extending our reach to accelerate growth,” said Swan. “With significant progress made across those priorities, we’re now at the right juncture to make this transition to the next leader of Intel. I am fully supportive of the board’s selection of Pat and have great confidence that, under his leadership and the rest of the management team, Intel will continue to lead the market as one of the world’s most influential technology companies.”

Monday, January 11, 2021

Intel leverages silicon photonics for Mobileye's lidar system-on-chip

Mobileye, a division of Intel, unveiled a new silicon photonics processor for frequency-modulated continuous wave (FMCW) lidar. The new device, which was engineered at Intel’s silicon photonics fab in New Mexico, is expected to be in production by 2025. 

Mobileye envisions that AVs will use both radio- and light-based detection-and-ranging sensing.

The new software-defined imaging radar technology with 2304 channels, 100DB dynamic range and 40 DBc side lobe level that together enable the radar to build a sensing state good enough for driving policy supporting autonomous driving. 

“This is really game-changing. And we call this a photonic integrated circuit, PIC. It has 184 vertical lines, and then those vertical lines are moved through optics. Having fabs that are able to do that, that’s very, very rare. So this gives Intel a significant advantage in building these lidars,” stated Mobileye president and chief executive officer Amnon Shashua.

https://newsroom.intel.com/news-releases/ces-2021-mobileye-avs-on-move/

Intel shows bevy of new processors

Intel introduced four new processors families - a total of more than 50 individual processor designs - for laptops and PCs.

At the high-end, the new 11th Gen Intel Core vPro processors feature hardware security to detect and stop ransomware and crypto-mining attacks. It is also equipped with Intel Control Flow Enforcement Technology, ground-breaking technology to help shut down an entire class of attacks that long evaded software-only solutions. This processor line leverages Intel 10-nanometer (nm) SuperFin technology, Intel Iris Xe graphics, and integrated Intel Wi-Fi 6/6E (Gig+).

Additionally, Intel demonstrated “Alder Lake,” the next-generation in x86 architecture and Intel’s most power-scalable system-on-chip.  Alder Lake will combine high-performance cores and high-efficiency cores into a single product. Alder Lake will also be Intel’s first processor built on a new, enhanced version of 10nm SuperFin. Intel expects to ship Alder Lake in the second half of 2021.

“Only Intel has the breadth of products spanning multiple architectures; the large, open ecosystem; sheer scale of manufacturing footprint; and deep technical expertise customers need to unlock opportunities in this era of distributed intelligence,” said Intel Executive Vice President Gregory Bryant.

Wednesday, January 6, 2021

Intel intros facial authentication solution

Intel introduced an on-device, facial authentication solution that combines an active depth sensor with a specialized neural network. The technology could be used for smart locks, access control, point-of-sale, ATMs, kiosks, etc.

Intel said its RealSense ID technology integrates anti-spoofing features and can adapt to users over time as they change physical features, such as facial hair and glasses. 

"Intel RealSense ID combines purpose-built hardware and software with a dedicated neural network designed to deliver a secure facial authentication platform that users can trust," said Sagi Ben Moshe, Intel corporate vice president and general manager of Emerging Growth and Incubation.

https://newsroom.intel.com/news/introducing-intel-realsense-id-facial-authentication

Thursday, December 17, 2020

Intel and Samsung achieve 5G SA Core capacity of 305 Gbps / server

Samsung and Intel achieved a record 5G SA Core data processing capacity of 305 Gbps per server – equivalent to hosting more than 200,000 users simultaneously live-streaming standard definition videos – as well as latency improvement in a mobile network environment with commercial features enabled. 

To achieve this result, Samsung’s 5G SA Core used the 2nd generation Intel Xeon Scalable processor and the Intel Ethernet Network Adapter E810 with Enhanced Dynamic Device Personalization (DDP). The companies said the Intel Ethernet Network Adapter E810 with Enhanced DDP is capable of optimizing data distribution and transmission functions across the network adapter and the CPU cores, resulting in higher performance. Samsung and Intel were able to implement a simplified system configuration and boost packet processing and overall network performance.

“Through close collaboration with Intel, we were able to achieve an industry-leading performance with our 5G SA Core,” said Sohyong Chong, Senior Vice President and Head of Core Software R&D, Networks Business at Samsung Electronics. “Samsung’s cloud-native 5G SA Core, through its highly flexible and scalable design, will enable our customers to launch 5G services more swiftly and cost-effectively.”

“The transition to 5G Standalone Core is essential to achieve the full potential of 5G,” said Alex Quach, Vice President and General Manager, Wireline and Core Network Division, Intel Corporation. “This milestone achieved with Samsung is a verification of how strong industry collaboration and the use of innovative technologies can enhance performance to accelerate this transition and pave the way to new network and edge services.”

https://news.samsung.com/us/samsung-achieves-305gbps-5g-sa-core/

Monday, December 14, 2020

Intel to start assembly & test operations in Costa Rica

Intel will invest US$350 million over the next three years to start assembly & test operations in Costa Rica. Assembly and test operations will be carried out at the Intel Costa Rica campus in San Antonio de Belén and will start in the second half of 2021. 

"The existing infrastructure, the synergy with operations already in place at the site, our talent, the free-zone regime and the legal environment, have given Intel a favorable option to expand its assembly & test capacity to Costa Rica", said Ileana Rojas, General Manager at Intel Costa Rica.

With the start of operations, Intel Costa Rica joins the Kulim site in Malaysia, the Chengdu plant in China, and the site in Ho Chi Minh City, Vietnam, which are the only Intel sites to perform global assembly & test operations, turning Intel Costa Rica into the first Latin American country site to perform such process.

"The fact that Costa Rica has become stronger as a trustworthy destination for investment amid the pandemic is a very powerful signal. Furthermore, it shows that the country builds long-term relationships with investors, since we have over two decades of history working together with Intel. An investment of this size deepens Intel's footprint and opens very significant job opportunities for people with different work profiles who will be able to join worldwide exports produced by the Costa Rican talent", said Carlos Alvarado, President of Costa Rica.


Thursday, December 3, 2020

Intel shows micro-ring modulators, all-silicon photodetectors, multi-lambda lasers

Intel showcased a number of advancements in the field of optical interconnects, advancing its long-term ambition to bring optical I/O directly into silicon packages. During a virtual Intel Labs day presentatio, the company demonstrated advances in key technology building blocks, including with light generation, amplification, detection, modulation, complementary metal-oxide semiconductor (CMOS) interface circuits and package integration. 

Key technology building blocks showcased:

  • Micro-ring modulators: Conventional silicon modulators take up too much area and are costly to place on IC packages. By developing micro-ring modulators, Intel has miniaturized the modulator by a factor of more than 1,000, thereby eliminating a key barrier to integrating silicon photonics onto a compute package.
  • All-silicon photodetector: For decades, the industry has believed silicon has virtually no light detection capability in the 1.3-1.6um wavelength range. Intel showcased research that proves otherwise. Lower cost is one of the main benefits of this breakthrough.
  • Integrated semiconductor optical amplifier: As the focus turns to reducing total power consumption, integrated semiconductor optical amplifiers are an indispensable technology, made possible with the same material used for the integrated laser.
  • Integrated multi-wavelength lasers: Using a technique called wavelength division multiplexing, separate wavelengths can be used from the same laser to convey more data in the same beam of light. This enables additional data to be transmitted over a single fiber, increasing bandwidth density.
  • Integration: By tightly integrating silicon photonics and CMOS silicon through advanced packaging techniques, we can gain three benefits: lower power, higher bandwidth and reduced pin count. Intel is the only company that has demonstrated integrated multi-wavelength lasers and semiconductor optical amplifiers, all-silicon photodetectors, and micro-ring modulators on a single technology platform tightly integrated with CMOS silicon. This research breakthrough paves the path for scaling integrated photonics.

Intel said these advancements will enable future architectures that are more disaggregated, with multiple functional blocks such as compute, memory, accelerators and peripherals spread throughout the entire network and interconnected via optical and software in high-speed and low-latency links.

“We are approaching an I/O power wall and an I/O bandwidth gap that will dramatically hinder performance scaling. The rapid progress Intel is making in integrated photonics will enable the industry to fully re-imagine data center networks and architectures that are connected by light. We have now demonstrated all of the critical optical technology building blocks on one silicon platform, tightly integrated with CMOS silicon. Our research on tightly integrating photonics with CMOS silicon can systematically eliminate barriers across cost, power and size constraints to bring the transformative power of optical interconnects to server packages,” stated James Jaussi, senior principal engineer and director of PHY Lab, Intel Labs.

Without such advancements, Intel warns the industry will soon reach the practical limits of electrical I/O performance - what it calls an "I/O power wall".



Tuesday, December 1, 2020

AWS to deploy Intel's Gaudi AI accelerators in EC2 instances

AWS will begin offering EC2 instances with up to eight of Intel's Habana Gaudi accelerators for machine learning workloads.

Gaudi accelerators are specifically designed for training deep learning models for workloads that include natural language processing, object detection and machine learning training, classification, recommendation and personalization.

“We are proud that AWS has chosen Habana Gaudi processors for its forthcoming EC2 training instances. The Habana team looks forward to our continued collaboration with AWS to deliver on a roadmap that will provide customers with continuity and advances over time,” states David Dahan, chief executive officer at Habana Labs, an Intel Company.

ntel acquires Habana Labs for $2 billion - AI chipset

Intel has acquired Habana Labs, an Israel-based developer of programmable deep learning accelerators for the data center, for approximately $2 billion.

Habana’s Gaudi AI Training Processor is currently sampling with select hyperscale customers. Large-node training systems based on Gaudi are expected to deliver up to a 4x increase in throughput versus systems built with the equivalent number of GPUs. Gaudi is designed for efficient and flexible system scale-up and scale-out.

Additionally, Habana’s Goya AI Inference Processor, which is commercially available, has demonstrated excellent inference performance including throughput and real-time latency in a highly competitive power envelope. Gaudi for training and Goya for inference offer a rich, easy-to-program development environment to help customers deploy and differentiate their solutions as AI workloads continue to evolve with growing demands on compute, memory and connectivity.

Habana will remain an independent business unit and will continue to be led by its current management team. Habana will report to Intel’s Data Platforms Group, home to Intel’s broad portfolio of data center class AI technologies.

“This acquisition advances our AI strategy, which is to provide customers with solutions to fit every performance need – from the intelligent edge to the data center,” said Navin Shenoy, executive vice president and general manager of the Data Platforms Group at Intel. “More specifically, Habana turbo-charges our AI offerings for the data center with a high-performance training processor family and a standards-based programming environment to address evolving AI workloads.”

Habana Labs chairman Avigdor Willenz will serve as a senior adviser to the business unit as well as to Intel Corporation after Intel’s purchase of Habana.

“We have been fortunate to get to know and collaborate with Intel given its investment in Habana, and we’re thrilled to be officially joining the team,” said David Dahan, CEO of Habana. “Intel has created a world-class AI team and capability. We are excited to partner with Intel to accelerate and scale our business. Together, we will deliver our customers more AI innovation, faster.”


Interview: Habana Labs targets AI processors



Habana Labs, a start-up based in Israel with offices in Silicon Valley, emerged from stealth to unveil its first AI processor. Habana's deep learning inference processor, named Goya, is >2 orders of magnitude better in throughput & power than commonly deployed CPUs, according to the company. The company will offer a PCIe 4.0 card that incorporates a single Goya HL-1000 processor and designed to accelerate various AI inferencing workloads,...



Wednesday, November 11, 2020

Intel advances its oneAPI initiative across CPUs, GPUs, FPGAs

Intel's oneAPI industry initiative, which was first announced at SuperComputing 2019, marked a major milestone with the gold release of oneAPI toolkits. The oneAPI vision calls for a unified and simplified cross-architecture programming model without proprietary lock-in while enabling the integration of legacy code. This programming model would extend across CPUs, GPUs, FPGAs and other accelerators. 

Intel said its oneAPI toolkits take advantage of hardware capabilities and instructions such as Intel AVX-512 and Intel DL Boost on CPUs, along with features unique to XPUs. 

“Today is a key moment in our ambitious oneAPI and XPU journey. With the gold release of our oneAPI toolkits, we have extended the developer experience from familiar CPU programming libraries and tools to include our vector-matrix-spatial architectures. We are also launching our first data center GPU based on Xe-LP microarchitecture focused on the fast-growing cloud gaming and media streaming segments,” states Raja Koduri, Intel senior vice president, chief architect and general manager of Architecture, Graphics and Software.

Intel also debuted its first discrete graphics processing unit (GPU) for the data center based on the Xe-LP microarchitecture and designed specifically for high-density, low-latency Android cloud gaming and media streaming.

https://newsroom.intel.com/news/intel-xpu-vision-oneapi-server-gpu/#gs.ko621d

Intel shows its Ponte Vecchio GPU and oneAPI programming model

Intel unveiled its new general-purpose "Ponte Vecchio" GPU architecture for HPC/AI acceleration, along with its new oneAPI, a unified and scalable programming model for the era of HPC/AI convergence. The oneAPI industry initiative ains to deliver a unified and simplified programming model for application development across heterogenous processing architectures, including CPUs, GPUs, FPGAs and other accelerators. The oneAPI specification includes...


Monday, November 2, 2020

DISH adds Intel as a 5G infrastructure partner

 DISH will integrate Intel 5G infrastructure technology into its forthcoming virtualized, open Radio Access Network (O-RAN) 5G network deployment. Specifically, DISH has selected the Intel Xeon Scalable Processor, the Intel Ethernet 800 Series network adapter, the Intel vRAN Dedicated Accelerator ACC100 and Intel's FlexRAN software reference architecture for its deployments.

The companies are collaborating on the fully virtualized RAN, including radio reference designs, fronthaul optimization, hardware-based security, and blueprints for servers. The two companies are also collaborating to enable edge applications for enterprises and driving O-RAN standards, and are cooperating in the areas of data optimization and Machine Learning for future phases of the network buildout. 

"Intel has been a trusted advisor throughout the design of our O-RAN network, working in concert with our software vendors Mavenir, Altiostar, and many OEM hardware providers. We have tested several commercial off-the-shelf (COTS) designs from a large number of server vendors using Intel's O-RAN compliant FlexRAN architecture and are pleased by the maturity and power of the solutions, together with the cost benefits of COTS solutions," said Marc Rouanne, executive vice president and chief network officer, DISH. "We are using the power of the VMware abstraction solution and the ubiquity of Intel-based servers to load and mix different types of cloud-native workloads like distributed unit (DU), centralized unit (CU), virtual routers, mobile edge computing applications, and 5G Core containerized network functions."

"Fully-virtualized, cloud-native networks like the one DISH is building bring the same server economics that transformed the data center," said Dan Rodriguez, Intel corporate vice president and general manager of the Network Platforms Group. "We are excited to partner with DISH to lay the foundation for a truly agile network and have already begun working with our OEM partners who have designed FlexRAN-based servers to enable a variety of new innovative use cases and services."

http://www.newsroom.intel.com

ISH selects Blue Planet automation software for its 5G network

 DISH selected inventory and service order management software from Ciena's Blue Planet division to automate its 5G network.Blue Planet's software automation delivers real-time management of all inventory, enabling on-demand provisioning and faster rollout of customer network slices. “Blue Planet is a key component within our 5G platform, allowing us to dynamically manage all of our network inventory and service orders in real-time,” said...

DISH picks Nokia for cloud-native, 5G standalone core

DISH Network selected Nokia’s cloud-native, standalone Core software products to help it build the most advanced, disruptive, fully-automated, cloud-native 5G network in the U.S..The deal, which follows months of joint testing, includes subscriber data management, device management, packet core, voice and data core, as well as integration services. Nokia will also deliver additional cloud-native products that will provide 4G, 5G standalone and Voice...

VMware introduced its 5G Telco Cloud Platform, featuring Tanzu Kubernetes Grid - an embedded Kubernetes distribution - that will allow Communication Service Providers (CSPs) to reliably build, manage and run containerized workloads across private, telco, edge and public clouds. VMware said its new solution provides a cloud-first network architecture to accelerate 5G and edge innovation while delivering service agility, operational consistency and...

DISH selected VMware's Telco Cloud solution for its 5G, cloud-native Open Radio Access Network (O-RAN). VMware said its Telco Cloud will enable DISH to utilize software from leading vendors to optimize and accelerate its 5G network deployment. Additionally, it will provide DISH with enhanced automation, resiliency, security and flexibility. The VMware Telco Cloud provides an abstraction layer across multiple network domains and enables DISH to leverage...

DISH takes over Boost Mobile and its 9.3 million subscribers

T-Mobile US completed its previously announced divestiture of Sprint’s prepaid wireless business to DISH Network Corporation, fulfilling a commitment that T-Mobile and Sprint made to the Department of Justice and to the Federal Communications Commission as part of their merger process.' DISH paid $1.4 billion for the acquisition of Boost Mobile and its 9.3 million customers. DISH said it will continue to invest in the Boost Mobile brand. John Swieringa,...

DISH picks Fujitsu for 5G radio units and Altiostar for virtualized RAN

DISH confirmed a large purchase of 5G radio units (RUs) from Fujitsu and a multi-year agreement with Altiostar to deliver a cloud-native Open vRAN software solution. DISH, which is committed to use O-RAN architecture in its 5G network, will be utilizing Fujitsu's Low Band Tri-Band RU and Mid Band Dual-Band RU, both industry firsts for O-RAN radios, across the company's spectrum portfolio. In addition to radio units, Fujitsu will provide support...