Showing posts with label FPGA. Show all posts
Showing posts with label FPGA. Show all posts

Wednesday, August 21, 2019

Xilinx's Virtex UltraScale+ FPGA boasts 35 billion transistors

Xilinx has expanded its 16nm Virtex UltraScale+ family to now include the world's largest FPGA — the Virtex UltraScale+ VU19P.

The new VU19P FPGA boasts 35 billion transistors, the highest logic density and I/O count on a single device, according to Xilinx. The device could be used for enabling emulation and prototyping of tomorrow's most advanced ASIC and SoC technologies, as well as test, measurement, compute, networking, aerospace and defense-related applications.

The VU19P FPGA features 9 million system logic cells, up to 1.5 terabits per-second of DDR4 memory bandwidth and up to 4.5 terabits per-second of transceiver bandwidth, and over 2,000 user I/Os. It is 1.6X larger than its predecessor and what was previously the industry's largest FPGA — the 20 nm Virtex UltraScale 440 FPGA. 

"The VU19P enables developers to accelerate hardware validation and begin software integration before their ASIC or SoC is available," said Sumit Shah, senior director, product line marketing and management, Xilinx. "This is our third generation of world-record FPGAs. First was the Virtex-7 2000T, followed by the Virtex UltraScale VU440, and now the Virtex UltraScale+ VU19P. But this is more than silicon technology; we're providing robust and proven tool flows and IP to support it."

"Arm relies on Xilinx devices as part of our process for validating our next-generation processor IP and SoC technology," said Tran Nguyen, director of design services, Arm. "The new VU19P will further enable Arm, and many others in our ecosystem, to accelerate the design, development and validation of our most ambitious roadmap technologies."

The VU19P will be generally available in the fall of 2020.

https://www.xilinx.com/news/press/2019/xilinx-announces-the-world-s-largest-fpga-featuring-9-million-system-logic-cells.html

Monday, August 5, 2019

Intel ships FPGA acceleration card for HPE Gen10 servers

The new high-performance Intel FPGA Programmable Acceleration Card (Intel FPGA PAC) D5005 is now shipping now in the HPE ProLiant DL3809 Gen10 server.

The Intel FPGA PAC D5005 acceleration card, which is based on an Intel Stratix 10 SX FPGA, provides high-performance inline and lookaside workload acceleration to servers based on Intel Xeon Scalable processors using the Intel Acceleration Stack, which includes acceleration libraries and development tools. Initial workloads specifically developed for the Intel FPGA PAC D5005 accelerator card include:

  • AI (speech-to-text translation) from Myrtle
  • Network security from Algo-Logic
  • Image transcoding from CTAccel
  • Video transcoding from IBEX


Compared with the Intel programmable acceleration card with Intel Arria 10 GX FPGA, the Intel FPGA PAC D5005 accelerator card offers significantly more resources including three times the amount of programmable logic, as much as 32 GB of DDR4 memory (a 4x increase) and faster Ethernet ports (two 100GE ports versus one 40GE port). With a smaller physical and power footprint, the Intel PAC with Intel Arria 10 GX FPGA fits a broader range of servers, while the Intel PAC D5005 is focused on providing a higher level of acceleration.

“The HPE ProLiant Gen10 server family is the world’s most secure, manageable and agile server platform available on the market today. By integrating the Intel FPGA PAC D5005 accelerator into the HPE ProLiant DL380 Gen10 server, we are now delivering optimized configurations for an increasing number of workloads, including AI inferencing, big data and streaming analytics, network security and image transcoding. Combined with our broad portfolio of services from HPE Pointnext, we enable our customers to accelerate time-to-value and increase ROI,” stated Bill Mannel, vice president and general manager, HPC and AI, at Hewlett Packard Enterprise.

Intel launches FPGA-based accelerator for 5G core and vRAN
Intel is introducing an FPGA-based acceleration card for 5G core and virtualized radio access network solutions.

The Intel FPGA Programmable Acceleration Card N3000 is designed to accelerate network traffic for up to 100 Gbps and supports up to 9GB DDR4 and 144MB QDR IV memory for high-performance applications. Programmability and flexibility of an FPGA allow customers to create tailored solutions by utilizing reference IPs for networking function acceleration workloads such as vRAN, vBNG, vEPC, IPSec and VPP.

Affirmed Networks is using Intel’s FPGA PAC in a new solution for 5G core network (CN)/evolved packet core – a 200 Gbps/server that provides smart load balancing and CPU cache optimizations.

Rakuten, the soon to be the operator of Japan’s newest mobile network, is including Intel x86 and FPGA-based PAC for acceleration from the core to the edge to provide the first end-to-end cloud-native mobile network. Intel FPGA PAC N3000 is the distributed unit accelerator next to Intel® Xeon Scalable processor where Layer 1 functions, such as forward error correction and front haul transmission, are offloaded onto an Intel FPGA.

Tuesday, June 4, 2019

Achronix next-gen FPGAs leverage Rambus GDDR6 PHY

Achronix Semiconductor's next-generation Speedster7t FPGA family will use Rambus GDDR6 PHY for its top-end data rates.

Rambus says its GDDR6 PHY is the fastest memory IP on the market, at 16 Gbps. The Rambus GDDR6 PHY enables the communication to and from high-speed, high-bandwidth GDDR6 SDRAM memory, which is a high-performance memory solution that can be used in a variety of applications that require large amounts of data computation.

Rambus worked closely with Achronix on their package design, to support the eight GDDR6 IP controllers on the first Speedster7t device. Providing up to 4 Tbps of performance, the new Speedster 7t FPGAs include a new 2D network-on-chip (NoC) and a high-density array of new machine learning processors (MLP). Merging FPGA programmability with ASIC routing structures and compute engines, the Speedster7t family creates a new “FPGA+” class of technology, pushing the boundaries of high-performance compute acceleration.


Monday, May 20, 2019

Lattice’s MachX03D FPGA offers Hardware Root-of-Trust

Lattice Semiconductor has begun sampling its MachXO3D FPGA for securing systems against a variety of threats.

The MachXO3 FPGA devices are typically the “first-on/last-off” component on circuit boards.

Lattice Semiconductor said that by integrating security and system control functions, its device becomes the first link in a chain of trust that protects entire systems.

Key features of the new MachXO3D include:

  • Control function FPGA that provides 4K and 9K look-up tables for implementing logic that instantly configures at power up from on device flash memory
  • On-device regulator for single 2.5/3.3-volt power supply operation
  • Support for up to 2700 Kbits of user Flash memory and up to 430 Kbits sysMEM™ embedded block RAM to provide more flexible design options
  • Up to 383 I/Os, configurable to support LVCMOS 3.3 to 1.0, and designed to integrate into a wide variety of system environments with features such as hot-socketing, default pull-down, input hysteresis, and programmable slew rate
  • Embedded security block that provides pre-verified hardware support for cryptographic functions such as ECC, AES, SHA, PKC and Unique Secure ID
  • Embedded secure configuration engine to ensure only FPGA configurations from a trusted source can be installed
  • Dual on-device configuration memories to enable fail-safe reprogramming of component firmware in the event of compromise

“System developers commonly take advantage of FPGA flexibility to enhance system functions after deployment,” said Gordon Hands, Director of Solutions Marketing, Lattice Semiconductor. “With MachXO3D, we took care to retain that flexibility while adding a secure configuration block to deliver the industry’s first control-oriented FPGA compliant with NIST’s Platform Firmware Resilience specification.”

Sampling is underway.

http://www.latticesemi.com/MachXO3D

Tuesday, May 7, 2019

Ingram Micro adds Xilinx accelerator cards to catalog

Ingram Micro has been named a primary distributor for Xilinx's new Alveo data center accelerator cards.

Ingram Micro will distribute the Xilinx cards to channel partners throughout the United States. Xilinx said channel partners will help speed the deployment of the cards in industry standard servers, ultimately optimizing the solutions for customers’ shifting data center workloads, new standards and evolving algorithms.


  • In October, as part of its updated data center strategy, Xilinx announced its own portfolio of accelerator cards for industry-standard servers in cloud and on-premise data centers. The new Alveo PCIe cards are powered by the Xilinx UltraScale+ FPGA, are available now for production orders. Customers can reconfigure the hardware, enabling them to optimize for shifting workloads, new standards, and updated algorithms.


Tuesday, April 16, 2019

Intel acquires Omnitek for FPGA expertise

Intel has acquired Omnitek, a provider of optimized video and vision FPGA IP solutions based in Basingstoke, England. Financial terms were not disclosed.

Omnitek was founded in 1998 and has developed over 220 FPGA IP cores and accompanying software including performance-leading solutions for WARP, ISP processing and video connectivity. Omnitek enables customized high-performance vision and artificial intelligence (AI) inferencing capabilities on FPGAs for customers across a range of end markets.

“Omnitek’s technology is a great complement to our FPGA business. Their deep, system-level FPGA expertise and high-performance video and vision-related technology have made them a trusted partner for many of our most important customers. Together, we will deliver leading FPGA solutions for video, vision and AI inferencing applications on Intel FPGAs and speed time-to-market for our existing customers while winning new ones,” Dan McNamara, Intel senior vice president and general manager of the Programmable Solutions Group.

“From data centers to devices, compute-intensive applications like 8K video and artificial intelligence require a multitude of innovative compute engines. FPGA devices play an increasingly critical role, often complementing other processing architectures, and Intel is at the center of this revolution,” said Roger Fawcett, CEO of Omnitek. “Omnitek is excited and extremely proud to bring our intellectual property and engineers to join the talented team in Intel’s Programmable Solutions Group.”

Tuesday, April 2, 2019

Intel's 10nm Agilex FPGA targets embedded, network and data centers

Intel introduced its new  Intel an"Agilex" field programmable gate array (FPGA) family targetted at embedded, network and data center markets.

The Intel Agilex family combines FPGA fabric built on Intel’s 10nm process with innovative heterogeneous 3D SiP technology. This provides the capability to integrate analog, memory, custom computing, custom I/O, and Intel eASIC device tiles into a single package with the FPGA fabric.

Intel delivers a custom logic continuum with reusable IPs through a migration path from FPGA to structured ASIC. One API provides a software-friendly heterogeneous programming environment, enabling software developers to easily access the benefits of FPGA for acceleration.

Intel said the new product is the first FPGA to support Compute Express Link, a cache and memory coherent interconnect to future Intel Xeon Scalable processors.

Agilex also supports 2nd-generation HyperFlex Architecture, which offers up to 40 percent higher performance, or up to 40 percent lower total power compared with Intel Stratix 10 FPGAs. The new Agilex family is also the only FPGA supporting hardened BFLOAT16 and up to 40 teraflops of digital signal processor (DSP) performance (FP16). It also supports Peripheral component interconnect express (PCIe) Gen 5.

The Agilex transceiver supports up to 112 Gbps data rates. Advanced memory support includes DDR5, HBM, and Intel Optane DC persistent memory.

“The race to solve data-centric problems requires agile and flexible solutions that can move, store and process data efficiently. Intel Agilex FPGAs deliver customized connectivity and acceleration while delivering much needed improvements in performance and power1,2 for diverse workloads," stated Dan McNamara, Intel senior vice president, Programmable Solutions Group.

https://newsroom.intel.com/news/intel-driving-data-centric-world-new-10nm-intel-agilex-fpga-family/#gs.3lgdg8

Tuesday, February 5, 2019

Investment bank reduces latency with FPGA-based accelerator

Velocimetrics, which supplies flow tracking and real-time, in-stream performance analytics, is using acceleration technology from Napatech to reduce the tick-to-trade latency of a global Tier 1 investment bank in Europe.

After detailed analysis of the bank's complex trading platform, Velocimetrics' analytics identified bottlenecks and latencies which, once corrected, resulted in a reduction in tick-to-trade latency from 100μs (microseconds) to 10μs.

The project used the Napatech SmartNIC FPGA-based solution as a key component in the Velocimetrics suite of products.

Paul Spencer, COO of Velocimetrics, commented: "In trading, every bit of latency makes a huge difference to the bottom line, and slashing it by a factor of 10 is enormously significant and, of course, profitable for the client. Napatech and Velocimetrics have a long and successful partnership, and the joint solution uses an innovative combination of technology; the success experienced by the client with this deployment provides further evidence of the financial value provided."

Jarrod Siket, CMO of Napatech, said: "To meet today's business requirements and address increasing competition and changes in the equities trading marketplace, financial services companies need full, independent visibility of their network and systems, as well as internal and external network applications, to make the right business decisions. This requires advanced monitoring and analytics that can deliver results in near-real time to keep pace with the speed of equities trading."

Thursday, December 13, 2018

Microsemi intros FPGA burst mode receiver for 10G PON

Microsemi introduced its PolarFire FPGA burst mode receiver (BMR) for compact 10G PON OLTs.

The company said its new BMR solution enables customers to build OLTs in small form factor modules while drawing the lowest power in extreme thermal environments. The device supports small form factor pluggable (SFP) and 10 Gb SFP (XFP) footprints.

“The PolarFire FPGA BMR solution is a game changer for our clients designing 10G PON applications because it fundamentally changes the way they build, deploy and maintain systems,” said Shakeel Peera, vice president of FPGA marketing for Microchip’s Programmable Solutions business unit. “The combination of PolarFire FPGAs and the new BMR technology enables designers to build unique, proprietary solutions that address the key challenges of reducing power consumption and heat dissipation of PON equipment, while delivering the small formfactor their end customers are demanding to expand remote deployment choices for carriers.”

Complementary Microchip solutions include the new SY88029L burst mode limiting amplifier. With burst mode signal detect time of less than 7 nanoseconds, the SY88029L is the first limiting amplifier fully compliant with XGSPON and NGPON2 timing requirements.

http://www.microsemi.com/polarfirebmr

Tuesday, September 25, 2018

Intel adds to portfolio of FPGA programmable acceleration cards

Intel is expanding its line of field programmable gate array (FPGA) acceleration cards with a new model based on its most powerful Stratix 10 SX FPGA.

The card leverages the Acceleration Stack for Intel Xeon CPU with FPGAs, providing data center developers a robust platform to deploy FPGA-based accelerated workloads. Hewlett Packard Enterprise* will be the first OEM to incorporate the Intel PAC with Stratix 10 SX FPGA along with the Intel Acceleration Stack for Intel Xeon Scalable processor with FPGAs into its servers.


Tuesday, July 17, 2018

REFLEX launches 800G acceleration card based on Intel FPGA

Paris-based Reflex CES introduced a 800 GbE accelerator card powered by Intel's S GX FPGA. The board comes in different variants where clients can choose from different memory or FPGA densities.

This board features the largest Stratix 10 GX device with 2800 KLE and is designed for processing intensive and various data a Stratixalgorithms thanks to its unique mix of memory capabilities of DDR4 and QDR2+ modules. REFLEX CES has adopted the disruptive QSFP-DD technology for the optical interfaces, delivering up to 800GbE in total. This is combined with a huge storage capability using 3 SlimSAS interfaces at the rear of the board. The hardware is delivered with a custom passive heat-sink.

http://reflexces.com


Monday, May 14, 2018

Molex acquires BittWare for FPGA-based platforms

Molex has acquired BittWare, a provider of computing systems featuring field-programmable gate arrays (FPGAs) deployed in data center compute and network packet processing applications. Financial terms were not disclosed.

Bittware, which is based in Concord, NH, provides solutions based on FPGA technology from Intel (formerly Altera) and Xilinx. BittWare FPGA solutions are used in compute and data center, military and aerospace, government, instrumentation and test, financial services, broadcast and video applications. BittWare serves original equipment manufacture (OEM) customers.

“FPGA-based platforms have become a strategically important driver of machine learning, artificial intelligence, cybersecurity, network acceleration, IoT, and other megatrends. As a Molex subsidiary, now working with Nallatech, I believe we will have the critical mass to bring new resources, better processes, and economies of scale to our valued customers and this rapidly growing industry as a whole,” said Jeff Milrod, president and CEO of BittWare.

Wednesday, April 11, 2018

Intel ships FPGA-powered accelerator cards for Xeon servers

Intel's FPGA-powered accelerator cards are featured in a new range of Xeon processor-based servers coming from major OEM customers, including Dell EMC and Fujitsu.

Both Dell EMC and Fujitsu will incorporate a complete Intel hardware and software stack in their individual offerings, consisting of Intel Programmable Acceleration Cards with Arria 10 GX FPGA and the Intel Acceleration Stack for Intel Xeon Scalable processor with FPGAs.

“We are beginning our adoption of Intel Programmable Acceleration Card with Arria 10 GX FPGA with PRIMERGY server and engaging our priority customers. The FPGA acceleration benefits enable operators to tackle the opex constraints while still achieving scale, performance and adaptability,” said Kenichi Sakai, corporate executive officer and head of Data Center Platform Business Unit of Fujitsu.

Dell EMC PowerEdge R640, R740 and R740XD servers incorporating Intel FPGA acceleration are now available for volume deployment with more to come.

“We are at the horizon of a new era of data center computing as Dell EMC and Fujitsu put the power and flexibility of Intel FPGAs in mainstream server products,” said Reynette Au, vice president of marketing for the Intel Programmable Solutions Group. “We’re enabling our customers and partners to create a rich set of high-performance solutions at scale by delivering the benefits of hardware performance, all in a software development environment.”

Intel first announced sampling of the card in October 2017 with the promise to make it commercially available in 1H 2018.

Monday, December 18, 2017

Intel ships Stratix 10 MX FPGA with High Bandwidth Memory DRAM

Intel has begun commercial shipments of the industry's first field programmable gate array (FPGA) with integrated High Bandwidth Memory DRAM (HBM2). Several variants are now available including the Intel Stratix 10 GX FPGAs (with 28G transceivers) and the Intel Stratix 10 SX FPGAs (with embedded quad-core ARM processor).

The Intel Stratix 10 MX FPGAs offer up to 10 times the memory bandwidth when compared with standalone DDR memory solutions, according to the company, making them suitable as multi-function accelerators for high-performance computing (HPC), data centers, network functions virtualization (NFV), and broadcast applications. The new devices provide a maximum memory bandwidth of 512 gigabytes per second with the integrated HBM2.

The Intel Stratix 10 MX FPGAs are manufactured using the company's 14 nm FinFET process and state-of-the-art packaging technology, including Embedded Multi-Die Interconnect Bridge (EMIB) technology to integrate HBM2 with the monolithic FPGA fabric.

"To efficiently accelerate these workloads, memory bandwidth needs to keep pace with the explosion in data" said Reynette Au, vice president of marketing, Intel Programmable Solutions Group. "We designed the Intel Stratix 10 MX family to provide a new class of FPGA-based multi-function data accelerators for HPC and HPDA markets."

Wednesday, October 25, 2017

Intel ships Stratix 10 FPGA with ARM Cortex-A53

Intel has begun shipping a high-end FPGA family with an integrated quad-core ARM Cortex-A53. 

The ARM-based Intel Stratix 10 FPGA, which packs more than 1 million logic elements (MLE) with an integrated ARM processor, could serve multiple application categories, such as 5G wireless communication, software defined radios, secure computing for military applications, network function virtualization (NFV), and data center acceleration.

For NFV, Intel said its new FPGA can handle the high-speed data path while the integrated processors enable low latency transactions needed to manage flow tables for control plane processing. With hardware acceleration, Intel Stratix 10 SX FPGAs provide a heterogeneous computing environment to create optimized, low latency accelerators.

“With Stratix 10 SX, Intel reaffirms its ‘all in’ commitment to SoC FPGA devices combining integrated, flexible ARM cores with high-performance Intel Stratix® 10 FPGAs,” said Reynette Au, vice president of marketing, Intel Programmable Solutions Group. “We now provide a wide set of options for customer needing processors and FPGAs, with device offerings across the low-end, mid-range and now, high-end FPGA families, to enable their system designs.”

Tuesday, September 12, 2017

Huawei picks Xilinx FPGAs for Accelerated Cloud Server

Huawei has selected Xilinx Virtex UltraScale+ FPGAs to power their first FP1 instance as part of a new accelerated cloud service. The Huawei FPGA Accelerated Cloud Server (FACS) is a platform that enables users to develop, deploy and publish new FPGA-based services and applications on Huawei Public Cloud.

Xilinx said its FPGAs can provide a 10-50x speed-up for compute intensive cloud applications such as machine learning, data analytics, and video processing.  Xilinx FPGAs can be reconfigured in less than a second to a different design that is hardware optimized for its next workload.

"The Huawei FACS is a fully integrated hardware and software platform offering developer-to-deployment support with best-in-class industry tool chains and access to Huawei's significant FPGA engineering expertise," said Steve Langridge, Director, Central Hardware Institute, Huawei Canada Research Center.

The FPGA Accelerated Cloud Server now available on the Huawei Public Cloud.

http://www.hwclouds.com/product/fcs.html
http://www.huaweicloud.com

Monday, July 10, 2017

Baidu deploys Xilinx FPGAs for cloud acceleration

Xilinx announced that Baidu has deployed Xilinx FPGA-based application acceleration services into its public cloud, specifically for the Baidu FPGA Cloud Server, a new service that leverages Xilinx Kintex FPGAs, tools and the software required for hardware-accelerated data centre applications such as machine learning and data security.

The Baidu FPGA Cloud Server provides a complete FPGA-based hardware and software development environment, including hardware and software design examples, and is designed to help users quickly develop and migrate applications with reduced development costs.

The Baidu service is based on each FPGA instance serving as a dedicated acceleration platform that is not shared between instances or users. The design examples provided services including cover deep learning acceleration, encryption and decryption.

Xilinx claims that FPGA-enabled servers can deliver a 10x to 80x performance per watt advantage compared to CPU-only servers. In addition, as they are dynamically reconfigurable, Xilinx FPGAs can support a range of workloads, including machine learning, data analytics, security and video processing.



  • Separately, Baidu announced a partnership with Microsoft for its new open source autonomous driving platform, Apollo. Baidu unveiled Apollo in April, featuring cloud services, software and reference hardware/vehicle platforms, and expects the technology will be running on roads by late 2020.
  • In addition, Conexant, a provider of audio and voice technology solutions, announced it was collaborating with Baidu to release development kits and reference designs for device makers to develop far-field voice-enabled artificial intelligent (AI) devices running on Baidu's DuerOS platform. The development kits and reference designs will feature Conexant's CX20924 4-microphone and CX20921 2-microphone voice input processing solutions and DuerOS, a conversation-based AI system that enables access to a voice-activated digital assistant for mobile phones, TVs and other devices.

Tuesday, May 9, 2017

Flex Logix, developer of embedded FPGA technology, raises $5m

Flex Logix Technologies, headquartered in Mountain View, California, a supplier of embedded FPGA IP and software:

a.         Founded in March 2014 to develop solutions for reconfigurable RTL in chip and system designs employing embedded FPGA IP cores and software.

b.         Offering the EFLX technology platform designed to significantly reduce design and manufacturing risks, accelerate technology development and provide greater flexibility for customers' hardware.

c.         Which in October 2015 announced it had raised $7.4 million in a financing round was led by dedicated hardware fund Eclipse Ventures (formerly the Formation 8 hardware fund), with participation from founding investors Lux Capital and the Tate Family Trust.

Announced it has secured $5 million in Series B equity financing in a round led by existing investors Lux Capital and Eclipse Ventures, with participation from the Tate Family Trust.

Flex Logix stated that new funding will be used to expand its sales, applications and engineering teams to meet the growing customer demand for its embedded FPGA platform in applications including networking, government, data centres and deep learning.

Targeting chips in multiple markets, the Flex Logix EFLX platform can be used with networking chips with reconfigurable protocols, data centre chips with reconfigurable accelerators, deep learning chips with real-time upgradeable algorithms, base stations chips with customisable features and MCU/IoT chips with flexible I/O and accelerators. The company noted that EFLX is currently available for popular process nodes and is being ported to further process nodes based on customer demand.

The Flex Logix technology offers high-density blocks of programmable RTL in any size together with the key features customers require. The solution allows designers to customise a single chip to address multiple markets and/or upgrade the chip while in the system to meet to changing standards such as networking protocols. It also allows customers to update chips with new deep learning algorithms and implement their own versions of protocols in data centres.

Regarding the new funding, Peter Hebert, managing partner at Lux Capital, said, "I believe that Flex Logix's embedded FPGA has the potential to be as pervasive as ARM's embedded processors… the company's software and silicon are proven and in use at multiple customers, paving the way to become one of the most widely-used chip building blocks across many markets and for a range of applications".

While Pierre Lamond, partner at Eclipse Ventures, commented, "The Flex Logix platform is the… most scalable and flexible embedded FPGA solution on the market, delivering competitive advantages in time to market, engineering efficiency, minimum metal layers and high density… the patented technology combined with an experienced management team led by Geoff Tate, founding CEO of Rambus, position the company for rapid growth".


Monday, April 10, 2017

Microsemi integrates Athena Cryptographic Processor into FPGAs

Microsemi and The Athena Group, a supplier of security, cryptography, anti-tamper and signal processing IP cores, announced that Athena's TeraFire cryptographic microprocessor has been integrated into Microsemi's recently introduced PolarFire FPGA 'S class' family.

Athena's TeraFire cryptographic microprocessor technology is designed to address cybersecurity requirements for a range of industries via support for the most commonly used cryptographic algorithms, including those certified for military/government use by the U.S. NIST's Suite B, as well as those recommended in the U.S. Commercial National Security Algorithm (CNSA) suite. TeraFire also supports algorithms and key sizes commonly used in Internet communications protocols, such as TLS, IPSec, MACSec and KeySec.

Microsemi's secure, cost-optimised PolarFire FPGAs offer low power consumption at mid-range densities with 12.7 Gbit/s SerDes transceivers, as well as high reliability, and target applications including wireline access networks and cellular infrastructure, smart connected factory, functional safety and secure communications.

PolarFire FPGAs' transceivers also offer support for multiple serial protocols, making them suitable for communications applications with 10 Gigabit Ethernet, CPRI, JESD204B, Interlaken and PCIe. In addition, the ability to implement serial gigabit Ethernet (SGMII) on general purpose input/output (GPIO) enables multiple 1 Gigabit Ethernet links to be supported.

Microsemi noted that the TeraFire cryptographic microprocessor enables a significant improvement in built-in cryptographic capabilities compared to SRAM-based FPGAs and has been adopted by both defence and commercial customers as a result of its flexibility and efficiency.

Athena's TeraFire cryptographic microprocessors can operation at up to 200 MHz. The TeraFire core provides advanced countermeasures against side-channel analysis (SCA) techniques such as DPA and differential electro-magnetic analysis (DEMA) that could otherwise be used to extract secret keys from the device, with supported algorithms that use a secret or private key offered with countermeasures against SCA.

Microsemi's PolarFire 'S class' FPGAs equipped with Athena TeraFire cryptographic microprocessor are scheduled to be available by the end of the second quarter of 2017.

https://www.microsemi.com/

Friday, March 17, 2017

Xilinx to Demo FPGAs in 400G Ethernet, FlexE

At this week's Optical Fiber Communications (OFC) Conference and Exhibition in Los Angeles Xilinx will debut a number of solutions for high speed data center interconnect (DCI) solutions.

Xilinx will participate in a 400GE multi-vendor network demo featuring the world's first standards-based 400GE MAC and PCS IP in a Xilinx Virtex UltraScale+™ VU9P FPGA. Showcasing the emerging 400GE standard interoperability between multiple vendors, the demo illustrates the Xilinx 400G solution connecting to a Finisar 400GE CFP8 module which in turn connects to a Spirent 400G test module in the Ethernet Alliance booth.

Xilinx will also showcase a complete FlexE 1.0 solution with bonding, sub-rating and channelization on its UltraScale+ FPGAs. This solution demonstrates how multiple clients can be transported using FlexE and highlights the ability of FlexE to carry larger data pipes and match them to transport links for optimal utilization of the link budget. This solution allows network operators to maximize optical performance and lower operating costs over existing infrastructure.

A third demo shows how LLDP packets can be snooped on transport line cards to allow a SDN controller to build a network topology for automation integral to data center networks. It also shows the use of IEEE compliant MACsec to encrypt and authenticate the link for security. As more and more critical applications and data migrate to the cloud, MACsec provides data encryption and authentication to preserve privacy. Such a solution is mandatory in front of a traditional DSP to provide a complete DCI solution.

Another demonstration showcases Xilinx's new 56G PAM-4 transceiver test chip in 16nm FinFET delivering optimized performance for backplane and LR applications.

http://www.xilinx.com

See also