Showing posts with label DARPA. Show all posts
Showing posts with label DARPA. Show all posts

Thursday, April 9, 2020

Intel and Georgia Tech to lead DARPA project

Intel and the Georgia Institute of Technology have been selected to lead a Guaranteeing Artificial Intelligence (AI) Robustness against Deception (GARD) program team for the Defense Advanced Research Projects Agency (DARPA).

The goal of the GARD program is to establish theoretical ML system foundations that will not only identify system vulnerabilities and characterize properties to enhance system robustness, but also promote the creation of effective defenses. Through these program elements, GARD aims to create deception-resistant ML technologies with stringent criteria for evaluating their effectiveness.

The first phase of GARD will focus on enhancing object detection technologies through spatial, temporal and semantic coherence for both still images and videos.

Intel is the prime contractor in this four-year, multimillion-dollar joint effort to improve cybersecurity defenses against deception attacks on machine learning (ML) models.

“Intel and Georgia Tech are working together to advance the ecosystem’s collective understanding of and ability to mitigate against AI and ML vulnerabilities. Through innovative research in coherence techniques, we are collaborating on an approach to enhance object detection and to improve the ability for AI and ML to respond to adversarial attacks,” states Jason Martin, principal engineer at Intel Labs and principal investigator for the DARPA GARD program from Intel.

Thursday, November 21, 2019

Ayar Labs selected for Intel’s DARPA PIPES Project

Ayar Labs has been selected as Intel’s optical I/O solution partner for their recently awarded DARPA PIPES (Photonics in Package for Extreme Scalability) project.

The PIPES project aims to develop integrated optical I/O solutions co-packaged with next generation FPGA/CPU/GPU and accelerators in Multi-Chip Packages (MCP) to provide extreme data rates (input/output) at ultra-low power over much longer distances than supported by current technology. In the first phase of the project, the Ayar Labs TeraPHY chiplet will be co-packaged with an Intel FPGA using the AIB (Advanced Interconnect Bus) interface and Intel’s EMIB silicon-bridge packaging. “We’re seeing an explosion of Datacenter workloads that have an insatiable demand for bandwidth and the need to connect devices at rack-scale distances,” said Vince Hu, VP of Strategy and Innovation for Intel’s FPGA products. “The best way to do that is with optical interconnect and by using an Ayar Labs chiplet(s), we can achieve very high bandwidth at low latency and low power consumption.”

“Bringing optical connectivity all the way into the CPU/SOC package has long been one of the ‘Holy Grail’ projects in High Performance and Hyperscale Computing, as it unleashes the performance of ever more powerful computing and network processors and removes a major bottleneck and set of constraints in systems architecture and design,” said Charles Wuischpard, CEO of Ayar Labs, “Moreover, the energy consumed in moving data through a system is now very significant and growing, and the best way to manage that is to move the data optically from end to end. We are pleased to be selected by Intel as the optical solution for their DARPA PIPES project and look forward to a multi-year collaboration.”

The TeraPHY chiplet is manufactured on GLOBALFOUNDRIES' 45nm platform, which enabled Ayar Labs to build a monolithic, single-die solution that integrates both electrical and optical photonic circuits and devices on a single chip.

“We have worked in close collaboration with Ayar Labs to deliver a new class of integrated electronic, photonics solutions,” said Anthony Yu, vice president of Computing and Wired Infrastructure at GF. “Going forward, we’re excited to work with the pioneers at Ayar Labs to continue disrupting the market by combining our next generation 45nm platform, targeted to future CMOS-based photonics solutions, with their differentiated technology that will push the limits of chip communication bandwidth for high-performance computing, cloud and AI applications.”

Ayar Labs also announced customer sampling of its fully integrated TeraPHY chiplet starting in early Q1 2020.

http://www.ayarlabs.com

Wednesday, July 2, 2014

DARPA Develops Silicon Transmitter Operating in Millimeter-wave Range

The Defense Advanced Research Projects Agency (DARPA) announced an all-silicon, microchip-sized transmitter that operates at 94 GHz -- the first silicon-only SoC that has achieved such a high frequency, which falls in the millimeter-wave range.

Researchers with DARPA’s Efficient Linearized All-Silicon Transmitter ICs (ELASTx) program have now shown that silicon chips be used for high data rate, millimeter-wave wireless communications systems.  Conventionally, such systems have used gallium arsenide (GaAs) or gallium nitride (GaN) chips.

DARPA said its all-silicon SoC transmitter uses a digitally assisted power amplifier that dynamically adapts amplifier performance characteristics to changing signal requirements, and it can support a range of modulation formats.  Northrop Grumman Aerospace Systems supported the research program.

“This accomplishment opens the door for co-designing digital CMOS [complementary metal oxide semiconductors] and millimeter-wave capabilities as an integrated system on an all-silicon chip, which should also make possible new design architectures for future military RF systems,” said Dev Palmer, DARPA program manager.

http://www.darpa.mil/NewsEvents/Releases/2014/06/30.aspx