Showing posts with label DARPA. Show all posts
Showing posts with label DARPA. Show all posts

Tuesday, June 15, 2021

DARPA: Filtering out interference for next-gen wideband arrays

DARPA is pursuing a COmpact Front-end Filters at the ElEment-level (COFFEE) program that aims to develop a new class of integrable, high-frequency RF filters for next-generation wideband arrays. The idea is to build filters that operate over a wide range of frequencies that are also small enough to fit behind each element of a phased array.

“Wideband, digital-at-every-element AESAs are particularly compelling for applications like advanced radar, electronic warfare (EW), and communications,” said Dr. Benjamin Griffin, a program manager in the Microsystems Technology Office (MTO). “However, high bandwidth receivers often have a limited dynamic range, leaving them vulnerable to electronic jamming. Further, digital-at-every-element exposes each element to interferers and requires filtering at the element level, leaving very little room to integrate conventional filter technologies.”

COFFEE is a part of DARPA’s Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the advancement of the U.S. semiconductor industry. 

https://www.darpa.mil/news-events/2021-06-10

Sunday, March 21, 2021

DARPA seeks to boost domestic manufacturing of structured ASICs

The U.S. Defense Advanced Research Projects Agency (DARPA) is launching an industry collaboration with Intel to expand access to domestic manufacturing capabilities for custom chips for defense systems. 

DARPA's Structured Array Hardware for Automatically Realized Applications (SAHARA) program is partnership with Intel and academic researchers from University of Florida, University of Maryland, and Texas A&M to develop U.S.-based manufacturing capabilities to enable the automated and scalable conversion of defense-relevant field-programmable gate array (FPGAs) designs into quantifiably secure Structured ASICs. 

SAHARA will also explore novel chip protections to support the manufacturing of silicon in zero-trust environments. While FPGAs are widely used in military applications today, Structured ASICs deliver significantly higher performance and lower power consumption.

For its part, Intel said it will use its structured ASIC technology to develop platforms that significantly accelerate development time and reduce engineering cost compared to traditional ASICs. 

Intel plans to manufacture these chips using its 10nm process technology with the advanced interface bus die-to-die interconnect and embedded multi-die interconnect bridge packaging technology to integrate multiple heterogenous die in a single package.

Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs. 

"We are combining our most advanced Intel eASIC structured ASIC technology with state-of-the-art data interface chiplets and enhanced security protection, and it’s all being made within the U.S. from beginning to end. This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10nm semiconductor process," stated José Roberto Alvarez, senior director, CTO Office, Intel Programmable Solutions Group.

SAHARA is a critical program supporting the Department of Defense (DoD) microelectronics Roadmap led by the Under Secretary of Defense for Research and Engineering – USD(R&E) – to define, quantify, and standardize security while strengthening domestic semiconductor manufacturing. The Rapid Assured Microelectronics Prototypes-Commercial (RAMP-C) and State-of-the-Art Heterogeneous Integration Prototype (SHIP) projects are also integral to the DoD Roadmap.

“The structured ASIC platforms and methods developed in SAHARA together with the advanced packaging technology developed in SHIP will enable the U.S. Department of Defense to more quickly and cost effectively develop and deploy advanced microelectronic systems critical to DoD modernization priorities,” said Brett Hamilton, deputy principal director for Microelectronics in USD(R&E).

https://www.darpa.mil/news-events/2021-03-18

Lattice Semiconductor joins DARPA Toolbox Initiative

Lattice Semiconductor's Diamond and FPGA design tools for its highly reliable, low-power, small form factor FPGAs are now included in the DARPA Toolbox initiative. The DARPA Toolbox initiative is a new, agency-wide effort aimed at providing access to state-of-the-art technology from leading commercial technology vendors to the researchers behind DARPA programs.The partnership also provides DARPA organizations with access to a selection of Lattice's...

DARPA launches Data Protection in Virtual Environments

The U.S. Defense Advanced Research Projects Agency (DARPA) launched an initiative called the Data Protection in Virtual Environments (DPRIVE) program which seeks to develop a hardware accelerator for Fully Homomorphic Encryption (FHE).Fully homomorphic encryption enables users to compute on always-encrypted data, or cryptograms. The data never needs to be decrypted, reducing the potential for cyberthreats.DPRIVE aims to design and implement a hardware...

The Defense Advanced Research Projects Agency (DARPA) reached an agreement with The Linux Foundation to create open source software that accelerates United States government technology research and development innovation.Specifically, DARPA and the LF will create a broad collaboration umbrella (US Government Open Programmable Secure (US GOV OPS) that allows United States Government projects, their ecosystem, and open community to participate in accelerating...

ONF's Aether Edge Cloud selected for DARPA's Pronto Project

The Open Networking Foundation's Aether 5G Connected Edge Cloud platform is being used as the software platform for Pronto, a project backed by $30 million in DARPA funding to develop secure 5G network infrastructure. Specifically, DARPA is funding ONF to build, deploy and operate the network to support research by Cornell, Princeton and Stanford universities in the areas of network verification and closed-loop control. Aether (pronounced ‘ee-ther’)...

DARPA backs Lasers for Universal Microscale Optical Systems program

DARPA is backing a new Lasers for Universal Microscale Optical Systems (LUMOS) program, which aims to bring high-performance lasers to advanced photonics platforms. Three LUMOS Technical Areas are cited:bringing high-performance lasers and optical amplifiers into advanced domestic photonics manufacturing foundries. Tower Semiconductor and SUNY Polytechnic Institute were selected to demonstrate flexible, efficient on-chip optical gain in their...


Monday, March 15, 2021

Lattice Semiconductor joins DARPA Toolbox Initiative

Lattice Semiconductor's Diamond and FPGA design tools for its highly reliable, low-power, small form factor FPGAs are now included in the DARPA Toolbox initiative. 

The DARPA Toolbox initiative is a new, agency-wide effort aimed at providing access to state-of-the-art technology from leading commercial technology vendors to the researchers behind DARPA programs.

The partnership also provides DARPA organizations with access to a selection of Lattice's soft IP cores and technical support to accelerate technology innovation for DARPA programs and foster the use of Lattice low-power FPGAs in DARPA-designed applications. 

“Partnering with technology innovators like Lattice through our DARPA Toolbox initiative serves to streamline access for our organizations to cutting-edge technologies,” said Serge Leef, the Microsystems Technology Office (MTO) program manager at DARPA and leader of the DARPA Toolbox initiative. “Lattice's portfolio of FPGA design tools and soft IP cores offer a compelling platform for our researchers to consider when implementing applications requiring artificial intelligence at the Edge, 5G communications, and/or automation."

Monday, March 8, 2021

DARPA launches Data Protection in Virtual Environments

The U.S. Defense Advanced Research Projects Agency (DARPA) launched an initiative called the Data Protection in Virtual Environments (DPRIVE) program which seeks to develop a hardware accelerator for Fully Homomorphic Encryption (FHE).

Fully homomorphic encryption enables users to compute on always-encrypted data, or cryptograms. The data never needs to be decrypted, reducing the potential for cyberthreats.

DPRIVE aims to design and implement a hardware accelerator for FHE computations that is capable of drastically speeding up FHE calculations, making the technology more accessible for sensitive defense applications as well as commercial use.

DARPA has selected four teams of researchers to lead the initiative: Duality Technologies, Galois, SRI International, and Intel Federal. Each team will develop an FHE accelerator hardware and software stack that reduces the computational overhead required to make FHE calculations to a speed comparable to similar unencrypted data operations. The teams will create accelerator architectures that are flexible, scalable, and programmable, but will also explore various approaches with different native word sizes. Current standard CPUs are based on 64-bit words, which are the units of data that determine a particular processor’s design. Word size directly relates to the signal-to-noise ratio of how encrypted data is stored and processed, as well as the error generated each time an FHE calculation is processed. The selected DPRIVE research teams will explore various approaches covering a diversity of word sizes – from 64 bits to thousands of bits – to solve the challenge.

In addition, teams are exploring novel approaches to memory management, flexible data structures and programming models, and formal verification methods to ensure the FHE implementation is correct-by-design and provides confidence to the user. As the co-design of FHE algorithms, hardware, and software is critical to the successful creation of the target DPRIVE accelerator, each team is bringing varied technical expertise to the program as well as in-depth knowledge on FHE.

“We currently estimate we are about a million times slower to compute in the FHE world then we are in the plaintext world. The goal of DPRIVE is to bring FHE down to the computational speeds we see in plaintext. If we are able to achieve this goal while positioning the technology to scale, DPRIVE will have a significant impact on our ability to protect and preserve data and user privacy,” concluded Rondeau.

“Fully homomorphic encryption remains the holy grail in the quest to keep data secure while in use. Despite strong advances in trusted execution environments and other confidential computing technologies to protect data while at rest and in transit, data is unencrypted during computation, opening the possibility of potential attacks at this stage. This frequently inhibits our ability to fully share and extract the maximum value out of data. We are pleased to be chosen as a technology partner by DARPA and look forward to working with them as well as Microsoft to advance this next chapter in confidential computing and unlock the promise of fully homomorphic encryption for all,” stated Rosario Cammarota, principal engineer, Intel Labs, and principal investigator, DARPA DPRIVE program.

For its part, Intel says it plans to design an application-specific integrated circuit (ASIC) accelerator to reduce the performance overhead currently associated with fully homomorphic encryption. When fully realized, the accelerator could deliver a massive improvement in executing FHE workloads over existing CPU-driven systems, potentially reducing cryptograms’ processing time by five orders of magnitude.

With its expertise in cloud infrastructure, software stacks and fully homomorphic encryption, Microsoft will be a critical partner in accelerating the commercialization of this technology when ready, enabling free data sharing and collaboration while promoting privacy throughout the data life cycle.

“We are pleased to bring our expertise in cloud computing and homomorphic encryption to the DARPA DPRIVE program, collaborating with Intel to advance this transformative technology when ready into commercial usages that will help our customers close the last-mile gap in data confidentiality —– keeping data fully secure and private, whether in storage, transit or use,” said Dr. William Chappell, chief technology officer, Azure Global, and vice president, Mission Systems, Microsoft.


Wednesday, February 17, 2021

DARPA teams with Linux Foundation to create secure open source

The Defense Advanced Research Projects Agency (DARPA) reached an agreement with The Linux Foundation to create open source software that accelerates United States government technology research and development innovation.

Specifically, DARPA and the LF will create a broad collaboration umbrella (US Government Open Programmable Secure (US GOV OPS) that allows United States Government projects, their ecosystem, and open community to participate in accelerating innovation and security in the areas of 5G, Edge, AI, Standards, Programmability, and IOT among other technologies. The project formation encourages ecosystem players to support US Government initiatives to create the latest in technology software.

The new US GOV OPS umbrella will include the Open Programmable Secure- 5G (OPS-5G) program as its first project, currently in formation with the help of DARPA, the US Navy and additional performers. The goal of OPS-5G is to create open source software and systems enabling secure end to end 5G and follow-on mobile networks. OPS-5G will create capabilities to address feature velocity in open source software, mitigating large scale Botnet of Things (BoT), network slicing on suspect gear, and adaptive adversaries operating at scale.

The project will launch as a standard open source project with neutral governance and a charter similar to other projects within the Linux Foundation. Additionally, the agreement enables collaboration with upstream and downstream communities such as LF Networking, LF Edge, and Zephyr, among others, to build on a secure code base for use by the US Government.

“DARPA’s use of open source software in the Open Programmable Secure 5G (OPS-5G) program leverages transparency, portability and open access inherent in this distribution model,” said Dr. Jonathan Smith, DARPA Information Innovation Office Program Manager. “Transparency enables advanced software tools and systems to be applied to the code base, while portability and open access will result in decoupling hardware and software ecosystems, enabling innovations by more entities across more technology areas.” 

“We are eager to ally with DARPA and its intent to accelerate secure, open source innovation and US competitiveness across breakthrough technologies,” said Arpit Joshipura, general manager, Networking, Edge, & IOT, the Linux Foundation. “This partnership enables transformational change across open software and systems, leveraging the best shared resources across the ecosystem.” 

http://www.usgovops.org

DARPA’s Electronics Resurgence Initiative signs Arm

Arm today announced a three-year partnership agreement with the U.S. Defense Advanced Research Projects Agency (DARPA), establishing an access framework to all commercially available Arm technology.

Under DARPA’s Electronics Resurgence Initiative, the research community that supports DARPA’s programs will gain access to Arm’s IP, tools and support programs.

“The span of DARPA research activity opens up a huge range of opportunities for future technological innovation,” said Rene Haas, president, IP Products Group, Arm. “Our expanded DARPA partnership will provide them with access to the broadest range of Arm technology to develop compute solutions supported by the world’s largest ecosystem of tools, services and software.”

“DARPA’s programs within the Microsystems Technology Office (MTO) focus on the most advanced challenges in microelectronics; equipping our community with best in class technologies is essential not only for break-through scientific and engineering advances, but also for improved transition into military and commercial applications,” stated Serge Leef, who leads design automation and secure hardware programs in MTO.

https://www.darpa.mil/work-with-us/electronics-resurgence-initiative

Thursday, December 3, 2020

DARPA backs Lasers for Universal Microscale Optical Systems program

DARPA is backing a new Lasers for Universal Microscale Optical Systems (LUMOS) program, which aims to bring high-performance lasers to advanced photonics platforms. 

Three LUMOS Technical Areas are cited:

  • bringing high-performance lasers and optical amplifiers into advanced domestic photonics manufacturing foundries. Tower Semiconductor and SUNY Polytechnic Institute were selected to demonstrate flexible, efficient on-chip optical gain in their photonics processes to enable next-generation optical microsystems for communications, computing, and sensing. LUMOS technologies will be made available to future design teams through DARPA-sponsored multi-project wafer runs.
  • developing high power lasers and amplifiers on fast photonics platforms for microwave applications. Research teams include Ultra-Low Loss Technologies, Quintessent, Harvard University, and Sandia National Laboratories.
  • creating precise lasers and integrated photonic circuits for visible spectrum applications with an ambitious goal of “wavelength by design” across an unprecedented spectral range. The teams will seek to develop lasers at many challenging wavelengths throughout the program to enable compact atomic sensors for navigation, precise timing solutions, and emerging quantum information hardware. Selected research teams include Nexus Photonics, Yale University, California Institute of Technology, Sandia National Laboratories, and the University of Colorado at Boulder.

"LUMOS is part of the third phase of DARPA’s Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems,” said Gordon Keeler, program manager in DARPA’s Microsystems Technology Office. “As an ERI program, LUMOS aims to create unique, differentiated domestic manufacturing capabilities that are accessible to the DoD through the enhanced capabilities of existing foundries and through DoD-relevant demonstration systems created by the program performers."

https://www.darpa.mil/news-events/2020-12-01

Thursday, August 20, 2020

DARPA’s Electronics Resurgence Initiative signs Arm

Arm today announced a three-year partnership agreement with the U.S. Defense Advanced Research Projects Agency (DARPA), establishing an access framework to all commercially available Arm technology.

Under DARPA’s Electronics Resurgence Initiative, the research community that supports DARPA’s programs will gain access to Arm’s IP, tools and support programs.

“The span of DARPA research activity opens up a huge range of opportunities for future technological innovation,” said Rene Haas, president, IP Products Group, Arm. “Our expanded DARPA partnership will provide them with access to the broadest range of Arm technology to develop compute solutions supported by the world’s largest ecosystem of tools, services and software.”

“DARPA’s programs within the Microsystems Technology Office (MTO) focus on the most advanced challenges in microelectronics; equipping our community with best in class technologies is essential not only for break-through scientific and engineering advances, but also for improved transition into military and commercial applications,” stated Serge Leef, who leads design automation and secure hardware programs in MTO.

https://www.darpa.mil/work-with-us/electronics-resurgence-initiative

Thursday, April 9, 2020

Intel and Georgia Tech to lead DARPA project

Intel and the Georgia Institute of Technology have been selected to lead a Guaranteeing Artificial Intelligence (AI) Robustness against Deception (GARD) program team for the Defense Advanced Research Projects Agency (DARPA).

The goal of the GARD program is to establish theoretical ML system foundations that will not only identify system vulnerabilities and characterize properties to enhance system robustness, but also promote the creation of effective defenses. Through these program elements, GARD aims to create deception-resistant ML technologies with stringent criteria for evaluating their effectiveness.

The first phase of GARD will focus on enhancing object detection technologies through spatial, temporal and semantic coherence for both still images and videos.

Intel is the prime contractor in this four-year, multimillion-dollar joint effort to improve cybersecurity defenses against deception attacks on machine learning (ML) models.

“Intel and Georgia Tech are working together to advance the ecosystem’s collective understanding of and ability to mitigate against AI and ML vulnerabilities. Through innovative research in coherence techniques, we are collaborating on an approach to enhance object detection and to improve the ability for AI and ML to respond to adversarial attacks,” states Jason Martin, principal engineer at Intel Labs and principal investigator for the DARPA GARD program from Intel.

Thursday, November 21, 2019

Ayar Labs selected for Intel’s DARPA PIPES Project

Ayar Labs has been selected as Intel’s optical I/O solution partner for their recently awarded DARPA PIPES (Photonics in Package for Extreme Scalability) project.

The PIPES project aims to develop integrated optical I/O solutions co-packaged with next generation FPGA/CPU/GPU and accelerators in Multi-Chip Packages (MCP) to provide extreme data rates (input/output) at ultra-low power over much longer distances than supported by current technology. In the first phase of the project, the Ayar Labs TeraPHY chiplet will be co-packaged with an Intel FPGA using the AIB (Advanced Interconnect Bus) interface and Intel’s EMIB silicon-bridge packaging. “We’re seeing an explosion of Datacenter workloads that have an insatiable demand for bandwidth and the need to connect devices at rack-scale distances,” said Vince Hu, VP of Strategy and Innovation for Intel’s FPGA products. “The best way to do that is with optical interconnect and by using an Ayar Labs chiplet(s), we can achieve very high bandwidth at low latency and low power consumption.”

“Bringing optical connectivity all the way into the CPU/SOC package has long been one of the ‘Holy Grail’ projects in High Performance and Hyperscale Computing, as it unleashes the performance of ever more powerful computing and network processors and removes a major bottleneck and set of constraints in systems architecture and design,” said Charles Wuischpard, CEO of Ayar Labs, “Moreover, the energy consumed in moving data through a system is now very significant and growing, and the best way to manage that is to move the data optically from end to end. We are pleased to be selected by Intel as the optical solution for their DARPA PIPES project and look forward to a multi-year collaboration.”

The TeraPHY chiplet is manufactured on GLOBALFOUNDRIES' 45nm platform, which enabled Ayar Labs to build a monolithic, single-die solution that integrates both electrical and optical photonic circuits and devices on a single chip.

“We have worked in close collaboration with Ayar Labs to deliver a new class of integrated electronic, photonics solutions,” said Anthony Yu, vice president of Computing and Wired Infrastructure at GF. “Going forward, we’re excited to work with the pioneers at Ayar Labs to continue disrupting the market by combining our next generation 45nm platform, targeted to future CMOS-based photonics solutions, with their differentiated technology that will push the limits of chip communication bandwidth for high-performance computing, cloud and AI applications.”

Ayar Labs also announced customer sampling of its fully integrated TeraPHY chiplet starting in early Q1 2020.

http://www.ayarlabs.com

Wednesday, July 2, 2014

DARPA Develops Silicon Transmitter Operating in Millimeter-wave Range

The Defense Advanced Research Projects Agency (DARPA) announced an all-silicon, microchip-sized transmitter that operates at 94 GHz -- the first silicon-only SoC that has achieved such a high frequency, which falls in the millimeter-wave range.

Researchers with DARPA’s Efficient Linearized All-Silicon Transmitter ICs (ELASTx) program have now shown that silicon chips be used for high data rate, millimeter-wave wireless communications systems.  Conventionally, such systems have used gallium arsenide (GaAs) or gallium nitride (GaN) chips.

DARPA said its all-silicon SoC transmitter uses a digitally assisted power amplifier that dynamically adapts amplifier performance characteristics to changing signal requirements, and it can support a range of modulation formats.  Northrop Grumman Aerospace Systems supported the research program.

“This accomplishment opens the door for co-designing digital CMOS [complementary metal oxide semiconductors] and millimeter-wave capabilities as an integrated system on an all-silicon chip, which should also make possible new design architectures for future military RF systems,” said Dev Palmer, DARPA program manager.

http://www.darpa.mil/NewsEvents/Releases/2014/06/30.aspx