Showing posts with label Cadence. Show all posts
Showing posts with label Cadence. Show all posts

Monday, April 22, 2019

Cadence says ready for TSMC’s 5nm FinFET

Cadence Design Systems confirmed that its digital, signoff and custom/analog tools have been certified for Design Rule Manual (DRM) and SPICE v1.0, and Cadence IP has been enabled for the TSMC 5nm process. The corresponding process design kits (PDKs) featuring integrated tools, flows and methodologies are now available for traditional and cloud-based environments. Additionally, mutual customers have already completed several tapeouts using Cadence tools, flows and IP for full production development on the TSMC 5nm process technology.

Cadence said it has delivered a fully integrated digital implementation and signoff tool flow, which has been certified on TSMC’s 5nm process that has the benefits of process simplification provided by extreme ultraviolet (EUV) lithography. The Cadence full-flow includes the Innovus Implementation System, Liberate Characterization Portfolio, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Pegasus™ Verification System.

“We’re continuing to broaden our collaboration with TSMC to facilitate 5nm FinFET adoption, giving customers access to the latest tools and IP for advanced process design creation,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Our R&D team has focused heavily on developing new features and performance improvements so that our digital and signoff and custom/analog tools and IP can be used with complete confidence, enabling customers to achieve first-pass silicon success and deliver end products within aggressive time-to-market schedules.”

http://www.cadence.com/go/tsmc5nmca


Monday, December 10, 2018

MaxLinear employs Cadence for 400Gbps PAM4 chip using 16FF

MaxLinear used Cadence timing signoff tools to deliver its MxL935xx Telluride device, the first 400Gbps PAM4 system on chip (SoC) using 16FF process technology.

Cadence said its Quantus Extraction Solution and Tempus Timing Signoff Solution were key enablers of the on-time delivery of working silicon for MaxLinear.

MaxLinear's Telluride device can be used by system vendors to develop a 400Gbps optical interconnect module in a compact form factor for intra-datacenter applications with a transmission distance up to 2 kilometers.

“Managing heavily congested and high-speed SoC design throughout the design flow with high-target utilization to reduce costs at 16FF node is a challenging task,” said Dr. Paolo Miliozzi, VP of SoC Technology, MaxLinear. “We are able to deploy the full-flow Cadence digital and signoff tool set including their Quantus, Tempus, and Tempus ECO solutions for successful signoff and on-time tapeout. Using these signoff engines, which are consistent with the Cadence Innovus Implementation System for both extraction and static timing analysis, ensured tight correlation and a reduction in design iterations during signoff for quick design convergence.”

Wednesday, September 19, 2018

Cadence intros deep neural-network accelerator AI processor IP

Cadence Design Systems introduced its deep neural-network accelerator (DNA) AI processor intellectual property for developers of articial intelligence semiconductors for use in applications spanning autonomous vehicles (AVs), ADAS, surveillance, robotics, drones, augmented reality (AR)/virtual reality (VR), smartphones, smart home and IoT.

The Cadence Tensilica DNA 100 Processor IP targets high performance and power efficiency across a full range of compute from 0.5 TeraMAC (TMAC) to 100s of TMACs. The company said processors based on this IP could deliver up to 4.7X better performance and up to 2.3X more performance per watt compared to other solutions with similar multiplier-accumulator (MAC) array sizes. Compatibility with the latest version of the Tensilica Neural Network Compiler enables support for advanced AI frameworks including Caffe, TensorFlow, TensorFlow Lite, and a broad spectrum of neural networks including convolution and recurrent networks. This makes the DNA 100 processor an ideal candidate for on-device inferencing for vision, speech, radar, lidar and co

“The applications for AI processors are growing rapidly, but running the latest neural network models can strain available power budgets,” said Mike Demler, senior analyst at the Linley Group. “Meeting the demands for AI capabilities in devices ranging from small, battery-operated IoT sensors to self-driving cars will require more efficient architectures. The innovative sparse compute engine in Cadence’s new Tensilica DNA 100 processor addresses these limitations and packs a lot of performance for any power budget.”


Tuesday, June 3, 2014

Cadence Collaborates with Intel on 14nm Tri-gate Design

Cadence Design Systems announced support for Intel’s 14nm Tri-Gate process technology to enable customers of Intel Custom Foundry. Cadence and Intel have together enabled the custom/analog flow, including Spectre APS, Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso Analog Design Environment for the 14nm Tri-Gate process. The companies are also collaborating on the development of the Cadence digital flow featuring Encounter Digital Implementation System, QRC Extraction Solution, and Tempus™ Timing Signoff Solution.

Cadence is also delivering the LPDDR4-3200 PHY for Intel Custom Foundry’s 14nm Low Power design platform. With data rates of up to 3200Mbps and a 1.6 GHz memory clock, this latest and most advanced memory PHY IP realizes the full capabilities of LPDDR4 technology. Cadence LPDDR4-3200 PHY IP is backward compatible with LPDDR3 memories and supports package on package (POP) and memory on PCB systems, making it ideal for the mobile market, which demands high memory performance, low power, low cost and compact systems.

http://www.cadence.com
http://www.intel.com

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