Showing posts with label Avicena. Show all posts
Showing posts with label Avicena. Show all posts

Wednesday, June 9, 2021

Avicena develops highly parallel optical interconnect for chips

Avicena, a start-up based in Mountain View, California, unveiled a highly parallel optical interconnect technology targeting up to 10 meters reach for chip-to-chip interconnects in distributed computing, processor-to-memory disaggregation, and other advanced computing applications. 

Avicena's LightBundle is based on arrays of novel GaN high-speed micro-emitters, leveraging the microLED display manufacturing ecosystem, and is fully compatible with high performance silicon ICs. The company has demonstrated an array of 200 CROME devices with a pitch of 30μm coupled to an array of PDs with a multi-core imaging fiber. Avicena says individual lanes show excellent performance characteristics up to a data rate of 10Gbps over the full temperature range of -40°C to 150°C. This extrapolates to an aggregate link bandwidth of 2Tbps for 200 lanes with a bandwidth density of 10Tbps/mm2.

“All of this is changing with the recent advances in optical emitter technology driven by advances in the display industry,” says Bardia Pezeshki, founder and CEO of Avicena. “We have developed very high-performance optical transmitters based on emitter technology from the display industry. These innovative devices would have been impractical just a few years ago. Our optimized devices and materials support 10Gbps links per lane over -40°C to +150°C temperature with excellent reliability. We refer to our new optical sources as Cavity-Reinforced Optical Micro-Emitters or CROMEs. We connect CROME arrays with CMOS compatible PDs using multi-core fiber bundles to create massively parallel interconnects with 1000s of parallel lanes over a reach of up to 10m. We call this new class of optical interconnect the Avicena LightBundleTM.”

The company says the parallel nature of its LightBundle technology is well-matched to parallel chiplet interfaces like AIB, HBI, and BoW, and can also be used to extend the reach of standard compute interconnects like PCIe, NVLink, and multi-channel G/DDR memory links with low power and low latency.