Showing posts with label Altera. Show all posts
Showing posts with label Altera. Show all posts

Monday, January 4, 2016

Intel Completes Acquisition of Altera

Intel completed its previously announced acquisition of Altera, a provider of field-programmable gate array (FPGA) technology.

Altera will operate as a new Intel business unit called the Programmable Solutions Group (PSG), led by Altera veteran Dan McNamara. Intel said it is committed to a smooth transition for Altera customers and will continue the support and future product development of Altera's many products, including FPGA, ARM-based SoC and power products. In addition to strengthening the existing FPGA business, PSG will work closely with Intel's Data Center Group and IoT Group to deliver the next generation of highly customized, integrated products and solutions.

"Altera is now part of Intel, and together we will make the next generation of semiconductors not only better but able to do more," said Brian Krzanich, Intel CEO. "We will apply Moore's Law to grow today's FPGA business, and we'll invent new products that make amazing experiences of the future possible – experiences like autonomous driving and machine learning."

http://www.intel.com

Intel to Acquire Altera for its Programmable Logic Devices

Intel agreed to acquire Altera a for $54 per share in an all-cash transaction valued at approximately $16.7 billion.

Altera, which is based in San Jose, California, offers programmable logic, process technologies, IP cores and development tools . Its portfolio includes its Stratix series FPGAs with embedded memory, digital signal processing (DSP) blocks, high-speed transceivers, and high-speed I/O pins. Altera's Arria system-on-chip solutions integrate an ARM-based hard processor and memory interfaces with the FPGA fabric using a high-bandwidth interconnect. These devices include additional hard logic such as PCI Express Gen2, multiport memory controllers, error correction code (ECC), memory protection and high-speed serial transceivers.

Altera had 2014 revenue of $1.9 billion, of which 44% of sales were for telecom/wireless, 22% for industrial/military/automotive, and 16% for networking/computer/storage. Altera holds about 39% market share of the PLD segment compared to 49% for Xilinx. The company was founded in 1983 and has approximately 3,000 employees.

"Intel's growth strategy is to expand our core assets into profitable, complementary market segments," said Brian Krzanich, CEO of Intel. "With this acquisition, we will harness the power of Moore's Law to make the next generation of solutions not just better, but able to do more. Whether to enable new growth in the network, large cloud data centers or IoT segments, our customers expect better performance at lower costs. This is the promise of Moore's Law and it's the innovation enabled by Intel and Altera joining forces."

"Given our close partnership, we've seen firsthand the many benefits of our relationship with Intel—the world's largest semiconductor company and a proven technology leader, and look forward to the many opportunities we will have together," said John Daane, President, CEO and Chairman of Altera. "We believe that as part of Intel we will be able to develop innovative FPGAs and system-on-chips for our customers in all market segments."

http://www.intel.com
http://www.altera.com
  • In February 2013, Altera announced that its next generation FPGAs will be based on Intel’s 14 nm tri-gate transistor technology. These next-generation products target ultra high-performance systems for military, wireline communications, cloud networking, and compute and storage applications. Under a partnership deal announced by the firms, Altera’s next-generation products will now include 14 nm, in addition to previously announced 20 nm technologies.

Saturday, October 10, 2015

Altera Demos FPGAs for CCAP Architecture

Altera demonstrated its new, flexible and upgradeable silicon solution for  multi-service operators (MSOs) adopting distributed CCAP (converged cable access platform) architecture.

The Altera DOCSIS Remote (MAC) PHY design, which is being demonstrated with partners Analog Devices, and Capacicom, enables cable operators to more efficiently and cost-effectively meet the ever-increasing need to segment cable networks, driven by the demand of high-speed Internet, unicast 4K video and other multimedia content.

The solution uses Altera Arria 10 FPGAs and Analog Devices' class-leading digital-to-analog converters (DACs) and analog-to-digital converters (ADCs), combined with Capacicom's MAC and PHY implementation, resulting in state-of-the-art radio frequency (RF) performance.

"With today's Altera FPGA portfolio and onward technology roadmap coupled with Capacicom's substantial experience in DOCSIS PHY and MAC layers, ADI has now found the perfect combination of partners to extend its leadership in high-performance analog into cable infrastructure solutions," said Carlton Lane, Analog Devices cable solutions manager. "ADI, Altera and Capacicom have set up a long-term collaboration to create the semiconductor industry reference platform for R - (MAC) PHY, with a continuing roadmap commitment to the lowest power consumption and cost per port."

Arria 10 FPGAs and SoCs deliver the highest performance at 20 nm.  The company said its Arria 10 FPGAs and SoCs are up to 40 percent lower power than previous generation FPGAs and SoCs and feature the industry's only hard floating-point digital signal processing (DSP) blocks with speeds up to 1,500 giga floating-point operations per second (GFLOPS).

http://www.altera.com/arria10

Thursday, July 23, 2015

Altera Cites Slowdown in Wireless Infrastructure

Altera reported second quarter sales of $414.2 million, down 5 percent from the first quarter of 2015 and down 16 percent from the second quarter of 2014. Second quarter net income was $70.3 million, $0.23 per diluted share, compared with net income of $94.9 million, $0.31 per diluted share, in the first quarter of 2015 and $127.0 million, $0.41 per diluted share, in the second quarter of 2014.

Altera said sales declined sequentially with Telecom and Wireless sales down sharply, attributable in large measure to the company's wireless business. With a few exceptions, there was broad growth across the remainder of the company. Gross margin was 69.4%, significantly improved from first quarter levels, as a result of favorable vertical market mix.

"Our wireless customers reduced demand on us this quarter, as expected, in reaction to continuing adverse market conditions. This pause in wireless spend more than offset growth across many of our vertical markets," said John Daane, president, chief executive officer, and chairman of the board. "The most important news for the second quarter was the June 1st announcement of an agreement for Intel to acquire Altera. Over the past several years we have worked closely with Intel, the world's largest semiconductor company and a proven technology leader. Through that interaction, we understand well the benefits this transaction will bring to our customers through development of innovative market-leading FPGAs and SoCs that will be enabled by Intel and Altera joining forces."

http://www.altera.com

Monday, June 1, 2015

Intel to Acquire Altera for its Programmable Logic Devices

Intel agreed to acquire Altera a for $54 per share in an all-cash transaction valued at approximately $16.7 billion.

Altera, which is based in San Jose, California, offers programmable logic, process technologies, IP cores and development tools . Its portfolio includes its Stratix series FPGAs with embedded memory, digital signal processing (DSP) blocks, high-speed transceivers, and high-speed I/O pins. Altera's Arria system-on-chip solutions integrate an ARM-based hard processor and memory interfaces with the FPGA fabric using a high-bandwidth interconnect. These devices include additional hard logic such as PCI Express Gen2, multiport memory controllers, error correction code (ECC), memory protection and high-speed serial transceivers.

Altera had 2014 revenue of $1.9 billion, of which 44% of sales were for telecom/wireless, 22% for industrial/military/automotive, and 16% for networking/computer/storage. Altera holds about 39% market share of the PLD segment compared to 49% for Xilinx. The company was founded in 1983 and has approximately 3,000 employees.

"Intel's growth strategy is to expand our core assets into profitable, complementary market segments," said Brian Krzanich, CEO of Intel. "With this acquisition, we will harness the power of Moore's Law to make the next generation of solutions not just better, but able to do more. Whether to enable new growth in the network, large cloud data centers or IoT segments, our customers expect better performance at lower costs. This is the promise of Moore's Law and it's the innovation enabled by Intel and Altera joining forces."

"Given our close partnership, we've seen firsthand the many benefits of our relationship with Intel—the world's largest semiconductor company and a proven technology leader, and look forward to the many opportunities we will have together," said John Daane, President, CEO and Chairman of Altera. "We believe that as part of Intel we will be able to develop innovative FPGAs and system-on-chips for our customers in all market segments."

http://www.intel.com
http://www.altera.com

  • In February 2013, Altera announced that its next generation FPGAs will be based on Intel’s 14 nm tri-gate transistor technology. These next-generation products target ultra high-performance systems for military, wireline communications, cloud networking, and compute and storage applications. Under a partnership deal announced by the firms, Altera’s next-generation products will now include 14 nm, in addition to previously announced 20 nm technologies.

Monday, April 6, 2015

Juniper Debuts Accelerated 40GbE Switch with Xeon and FPGA for Programmability

Juniper Networks introduced an application acceleration switch and a new packet flow accelerator module designed to deliver lower latency for financial networks.

The new QFX5100-AA application acceleration switch and QFX-PFA packet flow accelerator module, which build on Juniper's QFX product family, leverage Maxeler Technologies’ customizable software logic to significantly accelerate business-critical applications in latency-sensitive computing environments.

The new QFX5100-AA switch combines the Intel Xeon processor E3-1125C v2 with Broadcom switching silicon, and the QFX-PFA module based on the Altera multi-100G field-programmable gate array (FPGA). It is configured with 24 ports of 40GbE with 2 expansion slots for 4x40, or one double wide slot for the FPGA-based module. Customers can use Java to program the module for compute-intensive applications. Integration with Junos Space Network Director ensures automated and simple data center management from a single point of control.

“The possibilities of compute-integrated networking are transformative across a broad variety of financial services, including equities and commodities exchanges, market data providers, high-frequency trading, and credit processing. We see great potential in other sectors for this technology, including energy, research, education and large enterprises. With the introduction of Juniper Networks QFX5100-AA and QFX-PFA, we are delivering new computing capabilities within the data center network to ensure that our customers can make the most informed split-second investment decisions,” stated Andrew Bach, chief architect for Financial Services Team, Juniper Networks.

“Juniper Networks’ new switch, powered by the Intel Xeon processor E3-1125C v2, provides the performance and added intelligence needed to improve the ease of application integration. This solution, which embeds applications directly into the switch and utilizes the power of distributed computing, allows customers to take advantage of greatly improved performance,” said Sandra Rivera, vice president & general manager, Network Platforms Group, Intel

http://www.juniper.net

Monday, June 16, 2014

Altera Collaborates with Microsoft on Software Defined Data Centers

Microsoft Research is testing Altera's FPGAs to accelerate its Bing search engine and other cloud services.

Details on the project were disclosed in a research paper titled, “A Reconfigurable Fabric for Accelerating Large-Scale Data Center Services” that was presented by Microsoft at the 41st International Symposium on Computer Architecture (ISCA) in Minneapolis. (link to the paper is below)

Altera’s software defined data center technology offerings are based on the company’s high performance Stratix V and Arria 10 FPGAs, and next-generation Stratix 10 FPGAs and SoCs which are manufactured using the Intel 14 nm Tri-Gate process and feature Altera’s high-performance HyperFlex architecture.

The Microsoft paper describes a testbed of 1,632 servers accelerated by FPGAs and achieving a very significant reduction in latency compared with commodity servers.

“Altera FPGAs help Microsoft meet the challenging workload requirements of high performance computing, while they help data centers stay within necessary cost, power efficiency and space limits,” said Michael Strickland, director of the Compute and Storage business unit, Altera. “Adding fine-grained FPGA acceleration to the compute fabric advances data center capabilities beyond what commodity server designs can provide.”

http://newsroom.altera.com/press-releases/altera-microsoft-datacenter.htm
http://research.microsoft.com/pubs/212001/Catapult_ISCA_2014.pdf


  • In March 2014, Altera and Intel announced their collaboration on the development of multi-die devices that leverage Intel’s package and assembly capabilities and Altera’s programmable logic technology. The collaboration is an extension of the foundry relationship between Altera and Intel, in which Intel is manufacturing Altera’s Stratix 10 FPGAs and SoCs using the 14 nm Tri-Gate process.  The new collaboration targets multi-die devices that integrates monolithic 14 nm Stratix 10 FPGAs and SoCs with other advanced components, which may include DRAM, SRAM, ASICs, processors and analog components, in a single package. 

Wednesday, November 20, 2013

Altera Releases New 100G Ethernet and Interlaken IP Cores

Altera expanded its intellectual property (IP) portfolio with four additions: an ultra-high performance and ultra-low latency 100G Interlaken, 100G Ethernet, 40G Ethernet and 10G Ethernet IP.

The new Interlaken and Ethernet IP cores are optimized for use in Altera's high-performance Stratix V FPGAs as well as future Generation 10 FPGAs and SoCs. Customers today via early access software are using these best-in-class IP cores in 20 nm Arria 10 FPGA designs.

http://www.altera.com/bic_ip

Monday, October 7, 2013

Altera Collaborates on China Mobile's C-RAN Architecture

Altera is collaborating with China Mobile Research Institute (CMRI) on its Centralized Radio Access Network (C-RAN) architecture. The cloud-based C-RAN architecture aims to use cloud technology to centralize the baseband processing across a large-scale area. China Mobile is actively developing the C-RAN architecture in order to cost-effectively optimize its network based on various wireless standards including GSM (2G), TD-SCDMA (3G) and LTE (4G).

Altera announced that its FPGAs and intellectual property (IP) are being used as a development platform.  Altera is also providing technical support to verify future wireless architectures used in the cellular network of China Mobile.

“A C-RAN architecture addresses many of the challenges that carriers like China Mobile must deal with in this mobile internet era,” said Scott Bibaud,senior vice president and general manager of Altera’s Communications and Broadcast Division.

http://www.altera.com

Monday, April 8, 2013

Altera Demos 20 nm Transceiver at 32 Gbps

Altera is demonstrating the industry's first 20nm programmable device with 32-Gbps transceiver capabilities. The device is based on TSMC's 20SoC process technology.

Altera said its demo validates the performance capabilities of 20 nm silicon.

The transceiver technology will be integrated into Altera's 20 nm FPGA products, fabricated on TSMC's 20SoC process. These devices enable customers to design next-generation serial links with the lowest power consumption, fastest timing closure and the highest quality signal integrity.

Altera is currently shipping 28 nm FPGAs with monolithically integrated low-power transceivers operating at 28 Gbps.

http://www.altera.com/32gbps-20nm


Monday, October 8, 2012

Altera Intros 28 nm Midrange FPGA


Altera introduced its Arria V GZ variant FPGA featuring 36 backplane-capable transceivers that can operate at speeds up to 12.5 Gbps and enable of a variety of protocols. In addition, the variant features four separate DDR3 DIMM interfaces at 72 bits wide, operating at 1600 Mbps.


Altera said its Arria V GZ device is the first midrange FPGA supporting hardened PCI Express Gen3 protocol stacks as well as anti-tampering anc security features.




“Customers face many challenges when designing high-performance systems, including the need to balance power and performance while increasing bandwidth to off-chip memory,” said Patrick Dorsey, senior director of component product marketing at Altera Corporation. “The Arria V GZ variant provides both the high-speed serial transceivers and the external memory capability that designers need to build today’s bandwidth-hungry data processing systems.”


Soft intellectual property (IP)-based memory controllers allowing for maximum flexibility
Most digital signal processing (DSP) in a midrange FPGA for high integration
Industry-leading, anti-tamper features, including enhanced advanced encryption standard (AES) and easy-to-use on-board and off-board key programming>
About Arria V FPGAs

Thursday, September 13, 2012

Altera Announces 100G OTN Chip

Altera announced a single-chip, multi-rate OTN (optical transport network) muxponder solution for 100G network aggregation.

The new device is based on Altera’s 28-nm high-performance Stratix V FPGA, which enables developers to integrate emerging client types into their networks, such as 16G Fibre Channel.

The proliferation of 10G ports and the acceleration of networks from 40G towards 100G is driving operators to look for ways to minimize operational complexity by aggregating both legacy clients as well as 10G and 40G feeder networks into 100G for high-capacity transport.

Altera said its multi-rate muxponder solution addresses both data center and transport aggregation by flexibly supporting emerging clients, such as 16G Fibre Channel and 40G Ethernet along with various 10G clients.

"Altera's comprehensive portfolio of FPGA-based OTN solutions have been selected by eight of the top ten optical OEMs," said Dan Mansur, director of Altera’s communications division. “With our latest multi-rate muxponder IP solution, customers can customize their systems and target FPGA architectures that are optimized for their specific design requirements."

http://www.altera.com