Showing posts with label 112G. Show all posts
Showing posts with label 112G. Show all posts

Tuesday, November 17, 2020

Marvell announces first 112G 5nm SerDes

Marvell introduced the first 112G 5nm SerDes solution that has been validated in hardware. The company also confirmed that it has recently secured a new custom ASIC design win customer that will embed this new IP to build next generation top-of-rack (ToR) and spine switches for leading hyperscale data centers.

The Marvell 5nm SerDes solution doubles the bandwidth of current systems based on 56G while enabling the deployment of 112G I/Os. The device offers the ability to operate at 112G PAM4 across channels with >40dB insertion loss. The solution also delivers power reduction of more than 25% compared to 7nm, enabling systems with tight thermal/power constraints and helping to drive down total cost of ownership. The power reduction of Marvell's high-speed SerDes enables scale up of bandwidth within acutely constrained 5G applications.

Marvell plans to offer a complete product suite of PHYs, switches, data processor units (DPUs), custom server processors, controllers, accelerators and custom ASICs in 5nm, delivering end-to-end interoperable infrastructure solutions. This interoperability between Marvell components will allow customers to significantly reduce their product development and validation cycle time, and time-to-market.

"Our new 112G 5nm SerDes solution, with its industry-leading power, performance and area metrics is a true game changer and will help scale data infrastructure to meet growing interconnect requirements," said Sandeep Bharathi, senior vice president of Central Engineering at Marvell. "System performance is typically limited by bandwidth and power in most infrastructure applications, and our new 112G solution in 5nm addresses this by doubling the bandwidth, while reducing the overall I/O power."

"We are excited to bring this proven 112G SerDes to our custom ASIC partners looking for the highest throughput at the lowest power in the industry. Our customers in multiple markets have confirmed for us that this IP exceeds their system requirements for performance and power consumption," said Kevin O'Buckley, vice president and general manager of the ASIC BU at Marvell. "Leveraging this 5nm SerDes IP across our Marvell platform allows our customers to build entire interoperable data center, wireless and wired networking systems using Marvell standard products, customized standard products and full custom ASIC solutions."


Marvell to acquire Inphi for optical components business

Marvell Technology Group Ltd. agreed to acquire Inphi Corp. in a cash and stock transaction valued at approximately US$10 billion, consisting of $66 in cash and 2.323 shares of stock of the combined company for each Inphi share. Upon closing of the transaction, Marvell shareholders will own approximately 83% of the combined company and Inphi stockholders will own approximately 17% of the combined company.Inphi’s high-speed electro-optics target data...

Marvell intros a customizable ASIC program in 5nm

Marvell debuted a cutomizable ASIC targetting applications ranging from next generation 5G carriers, cloud data centers, enterprise and automotive. Marvell’s new ASIC solution enables a multitude of customization options and a differentiated approach with best-in-class standard product IP including Arm-based processors, embedded memories, high-speed SerDes, networking, security and a wide range of storage controller and accelerators in 5nm and below. With...


Wednesday, June 17, 2020

Rambus delivers 112G XSR/USR PHY on TSMC 7nm

Rambus announced the availability of its 112G XSR/USR PHY based on TSMC’s industry-leading 7nm process.

Applications for the 112G XSR/USR PHY  and chiplet architectures include next-generation 51.2 Terabit per second (Tbps) ASICs for network switches, where 112G XSR links will connect the digital switch ASIC die to CPO engines. In AI/ML and HPC SoCs, the 112G XSR PHY can be used to bridge purpose-built accelerator chiplets for natural language processing, video transcoding and image recognition. Another popular use case is the die disaggregation of large SoCs, hitting reticle size limits for manufacturable yields, into multiple smaller die connected using XSR links over organic substrate. Increasingly, these advanced applications are implemented on TSMC’s N7 process.

“This important milestone highlights Rambus’ leadership in high-speed SerDes enabling the industry’s highest value and most demanding applications,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “At an industry-leading power efficiency of sub-picojoule per bit, and unidirectional bandwidth approaching two terabit per second per millimeter, we are very proud to offer our 112G XSR/USR solution in partnership with TSMC.”

“We’re pleased with the availability of Rambus’ PHY on our N7 process technology to address the growing market need for low-power, high-performance chiplet architectures,” said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. “Our ongoing partnership with Rambus ensures that designers can meet next-generation requirements for performance and power efficiency in computing, AI/ML and networking using TSMC’s advanced process technologies.”

https://www.rambus.com/interface-ip/serdes/112g-xsr-phy

Wednesday, January 29, 2020

Inphi intros its 2nd gen 112Gbps SerDes in 7nm

Inphi released its second-generation, high performance 112Gbps SerDes IP solution in 7nm.

Inphi said its new Capella SerDes IP is designed to ensure high performance across the most demanding environments for network connectivity and data transmission.

The announcement builds on Inphi’s track record of having shipped over a million 56Gbps and 112Gbps ports to date.

“Delivering the next generation of SerDes IP technology is a significant milestone for Inphi and for the industry, as we enable ASIC and silicon product vendors to take advantage of our state-of-the-art Capella solution,” said Kumaran Siva, AVP, Networking Interconnect, Inphi. “With our 56Gbps Syrma IP and our new next-generation 112Gbps Capella IP offering, we are raising the bar for what is possible in networking and AI applications.”

Sunday, March 18, 2018

Credo demos 112G PAM4

Credo, a semiconductor company specializing in Serializer-Deserializer (SerDes) technology, demonstrated its low power, high-performance 112 GbpsPAM4 SerDes technology at OFC 2018.

For 112G per lambda optical connectivity (i.e., DR, DR4, FR4), Credo has delivered product solutions in TSMC 28nm.

For 112G electrical VSR and LR reaches, Credo has delivered the solutions in TSMC 16nm.  The conference starts today at the San Diego Convention Center, with exhibits taking place March 13–15.

“Credo’s ability to deliver leading edge performance at the industry’s lowest power in mature TSMC process nodes enables rapid time-to-market at a cost structure that will accelerate the transition to the 112G connectivity radix,” said Jeff Twombly, vice president of business development at Credo. “hyperscale cloud providers want to move to single lane rate 112G connectivity as soon as possible. We are aggressively working with strategic ecosystem partners for 2019 trials which will enable production scale ramping in 2020.”