Sunday, March 21, 2021

DARPA seeks to boost domestic manufacturing of structured ASICs

The U.S. Defense Advanced Research Projects Agency (DARPA) is launching an industry collaboration with Intel to expand access to domestic manufacturing capabilities for custom chips for defense systems. 

DARPA's Structured Array Hardware for Automatically Realized Applications (SAHARA) program is partnership with Intel and academic researchers from University of Florida, University of Maryland, and Texas A&M to develop U.S.-based manufacturing capabilities to enable the automated and scalable conversion of defense-relevant field-programmable gate array (FPGAs) designs into quantifiably secure Structured ASICs. 

SAHARA will also explore novel chip protections to support the manufacturing of silicon in zero-trust environments. While FPGAs are widely used in military applications today, Structured ASICs deliver significantly higher performance and lower power consumption.

For its part, Intel said it will use its structured ASIC technology to develop platforms that significantly accelerate development time and reduce engineering cost compared to traditional ASICs. 

Intel plans to manufacture these chips using its 10nm process technology with the advanced interface bus die-to-die interconnect and embedded multi-die interconnect bridge packaging technology to integrate multiple heterogenous die in a single package.

Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs. 

"We are combining our most advanced Intel eASIC structured ASIC technology with state-of-the-art data interface chiplets and enhanced security protection, and it’s all being made within the U.S. from beginning to end. This will enable defense and commercial electronics systems developers to rapidly develop and deploy custom chips based on Intel’s advanced 10nm semiconductor process," stated JosĂ© Roberto Alvarez, senior director, CTO Office, Intel Programmable Solutions Group.

SAHARA is a critical program supporting the Department of Defense (DoD) microelectronics Roadmap led by the Under Secretary of Defense for Research and Engineering – USD(R&E) – to define, quantify, and standardize security while strengthening domestic semiconductor manufacturing. The Rapid Assured Microelectronics Prototypes-Commercial (RAMP-C) and State-of-the-Art Heterogeneous Integration Prototype (SHIP) projects are also integral to the DoD Roadmap.

“The structured ASIC platforms and methods developed in SAHARA together with the advanced packaging technology developed in SHIP will enable the U.S. Department of Defense to more quickly and cost effectively develop and deploy advanced microelectronic systems critical to DoD modernization priorities,” said Brett Hamilton, deputy principal director for Microelectronics in USD(R&E).

https://www.darpa.mil/news-events/2021-03-18

Lattice Semiconductor joins DARPA Toolbox Initiative

Lattice Semiconductor's Diamond and FPGA design tools for its highly reliable, low-power, small form factor FPGAs are now included in the DARPA Toolbox initiative. The DARPA Toolbox initiative is a new, agency-wide effort aimed at providing access to state-of-the-art technology from leading commercial technology vendors to the researchers behind DARPA programs.The partnership also provides DARPA organizations with access to a selection of Lattice's...

DARPA launches Data Protection in Virtual Environments

The U.S. Defense Advanced Research Projects Agency (DARPA) launched an initiative called the Data Protection in Virtual Environments (DPRIVE) program which seeks to develop a hardware accelerator for Fully Homomorphic Encryption (FHE).Fully homomorphic encryption enables users to compute on always-encrypted data, or cryptograms. The data never needs to be decrypted, reducing the potential for cyberthreats.DPRIVE aims to design and implement a hardware...

The Defense Advanced Research Projects Agency (DARPA) reached an agreement with The Linux Foundation to create open source software that accelerates United States government technology research and development innovation.Specifically, DARPA and the LF will create a broad collaboration umbrella (US Government Open Programmable Secure (US GOV OPS) that allows United States Government projects, their ecosystem, and open community to participate in accelerating...

ONF's Aether Edge Cloud selected for DARPA's Pronto Project

The Open Networking Foundation's Aether 5G Connected Edge Cloud platform is being used as the software platform for Pronto, a project backed by $30 million in DARPA funding to develop secure 5G network infrastructure. Specifically, DARPA is funding ONF to build, deploy and operate the network to support research by Cornell, Princeton and Stanford universities in the areas of network verification and closed-loop control. Aether (pronounced ‘ee-ther’)...

DARPA backs Lasers for Universal Microscale Optical Systems program

DARPA is backing a new Lasers for Universal Microscale Optical Systems (LUMOS) program, which aims to bring high-performance lasers to advanced photonics platforms. Three LUMOS Technical Areas are cited:bringing high-performance lasers and optical amplifiers into advanced domestic photonics manufacturing foundries. Tower Semiconductor and SUNY Polytechnic Institute were selected to demonstrate flexible, efficient on-chip optical gain in their...


Singapore to deploy 5G standalone RAN sharing network with Nokia

Antina Pte. Ltd., a joint venture formed by mobile network operators M1 and StarHub in Singapore, have deployed the first 5G standalone RAN Sharing network in South East Asia.

Nokia will provide equipment from its  AirScale portfolio and CloudRAN solution to build the Radio Access Network (RAN) for the 5G SA infrastructure, utilizing the 3.5GHz spectrum band. Nokia will supply 5G base stations and its small cells solution for indoor coverage, as well as other radio access products. 


Nokia said its CloudRAN technology will provide Antina with the flexibility to meet customer demands in the evolving 5G era. Nokia’s NetAct network management, CloudBand Application Manager and CloudBand Infrastructure Software will streamline operations and securely manage Antina’s networks.

Tommi Uitto, President of Mobile Networks, Nokia, said: “This is an important win for Nokia that demonstrates our leadership in commercial-grade Cloud RAN as well as mobile operators’ trust in our capabilities for rapidly transitioning to 5G standalone networks. We look forward to supporting Antina in the deployment of a successful rollout of the 5G SA network in Singapore which aligns with the country’s vision of creating a world-class 5G infrastructure. We hope other global markets considering making the move to 5G SA will take note of Antina’s success.”

Xilinx shrinks its UltraScale+ FPGAs with TSMC's InFO packaging

Xilinx expanded its UltraScale+ portfolio for markets with new applications that require ultra-compact and intelligent edge solutions. 

The company's Artix and Zynq UltraScale+ devices are now available in TSMC’s state-of-the-art InFO (Integrated Fan-Out) packaging technology, which is up to 70% smaller than traditional chip-scale packaging. 

“Demand for compact, intelligent edge applications is driving the requirement for processing and bandwidth engines to not only provide higher performance, but also new levels of compute density to enable the smallest form factor systems,” said Sumit Shah, senior director, Product Line Management and Marketing at Xilinx. “The new cost-optimized additions to our UltraScale+ portfolio are powerful enhancements that leverage the architecture and production-proven technology of Xilinx’s UltraScale+ FPGAs and MPSoCs, which collectively have been deployed in millions of systems worldwide.”

The Artix UltraScale+ family is built on its production-proven FPGA architecture and is designed for a range of applications including machine vision with advanced sensor technology, high-speed networking, and ultra-compact “8K-ready” video broadcasting. 

Artix UltraScale+ devices deliver 16 Gbps transceivers to support emerging and advanced protocols in networking, vision, and video, while also delivering the highest DSP compute in its class.

Nokia vows 50% power savings for 5G mMIMO base stations by 2023

Nokia announced that its AirScale 5G mMIMO Base Station will achieve an average power consumption reduction of 50 percent by 2023.

The energy savings will be enabled by its next-generation System on Chip (SoCs) chipsets and 5G advanced sleep mode features which will help to optimize the base station energy usage. 


Nokia said it is committed to having one of the industry’s most energy-efficient product portfolios. It recently announced new Science Based Targets (SBTs) which fulfill its commitment to recalibrate in line with a 1.5°C global warming scenario.

Ari Kynäslahti, Head of Technology and Strategy at Nokia Mobile Networks, commented: “Nokia is committed to contributing to solving the world’s sustainability challenges and we do that by ensuring our technology is designed to be as energy-efficient as possible. This means using less energy during use and manufacture. Everything from our chipsets to our software and hardware is geared towards supporting this goal.” 

https://www.nokia.com/about-us/news/releases/2021/03/17/nokia-to-halve-5g-base-station-power-consumption-by-2023/


Azure commits to Availability Zones architecture

Microsoft has committed to using Availability Zones architecture in all of its data enter regions worldwide in order to improve resiliency.

An Azure datacenter region is made up of multiple data center facilities with redundant power, cooling, and networking.

Azure Availability Zones (AZs), comprising of a minimum of three zones, allow customers to spread their infrastructure and applications across discrete and dispersed datacenters for added resiliency and high availability.


In a blog post, Pradeep Nair Vice President, Microsoft Azure, says that by the end of the 2021, every country in which the company operates a datacenter region will include at least one region with Azure Availability Zones architecture. Additionally, every new datacenter region that Microsoft launches going forward will have AZs. 

Over the last 12 months, Microsoft enabled Availability Zones in five datacenter regions, including most recently in Brazil South.

https://azure.microsoft.com/en-us/blog/our-commitment-to-expand-azure-availability-zones-to-more-regions/

Fire at Renesas' Naka semiconductor fab halts production of 300mm wafers

Renesas Electronics Corporation was struck by a fire in the N3 Building (300mm line) of its Naka Factory (located in Hitachinaka, Ibaraki Prefecture) on March 19, 2021 at 2:47am.

The fire was extinguished on the same day and there no casualties to the employees and no damages to the building. However, Renesas said there was some damage to some of the utility equipment, including its pure water supply, the air conditioning system, as well as to some of the manufacturing equipment. The burned area is approximately 600m2, which is around 5% of the 12,000m2 clean room area of the first floor N3 Building, and the burned manufacturing equipment was 11 units, which is around 2% of the manufacturing equipment of the N3 Building. 


Production at N3 Building (300mm wafers) has temporarily halted while the company cleans the interior of the clean room and procures replacements of the burned equipment.

Renesas aims to resume production within one month. The financial impact from halting the N3 Building production is approximately 17 billion yen per month. 

In a press conference, company officials extended their apologies for the occurrence of the fire, the circumstances and the causes, as well as the outlook going forward. 

"We would like to give our sincerest apologies to neighboring residents, customers, partner companies, relevant authorities and all those involved for the trouble the fire caused,” said Hidetoshi Shibata, President & CEO of Renesas. “In addition, we would like to express our gratitude for the fire department and those who partook in the extinguishing of the fire.”

The production at N2 Building (200mm line) and the WT Building (wafer testing) is operating as usual.