Wednesday, September 25, 2019

COBO demos packet transmission between On-Board and MSA modules

At this week's ECOC 2019 in Dublin, the Consortium for On-Board Optics (COBO) showcased compliance boards built to its recently completed Module Compliance Board (MCB) and Host Compliance Board (HCB) specification. Members also demonstrated the latest developments of optical connectivity solutions for faceplate, backplane, module and co-packaged optics.

Of note, a COBO proof-of-concept switch was demonstrating error-free packet transmission between COBO modules, OSFP modules and QSFP-DD modules. The 400GBASE-SR8 connections were between all module form factors. The OSFP and QSFP-DD modules operated at 10W; whereas, the COBO module had a 30% power savings by operating at under 7W. The ability to place the COBO module closer to the switch ASIC greatly improved the signal integrity performance of the connection permitting the COBO module to use a clock and data recovery (CDR) chip instead of a digital signal processing (DSP) chip.

“Member collaboration has enabled COBO to offer the industry’s first live traffic demonstration of an on-board optics switch based upon COBO’s specification and demonstrating the improved power efficiency of on-board optics,” said Brad Booth, President of COBO.  “COBO members have worked diligently to develop an industry-first specification for on-board optical modules and compliance boards to lower the barrier to entry for implementing on-board optics.”

http://onboardoptics.org






Broadcom delivers dual 400G MACSec PHY

Broadcom is now shipping a dual 400G MACSec PHY with AES-256 designed to address security requirements for high speed interconnects in modern network infrastructure including hyper-scale, cloud, service provider and enterprise networks.

Broadcom's BCM81343 quadruples the switch bandwidth capability of the previous generation duall 100G MACSec PHY by offering dual 400G ports. The device supports the IEEE 1588 precision time protocol (PTP) providing accurate clock timing for time-sensitive transactions and mission-critical tasks.

BCM81343 Product Highlights

  • Dual 400GbE PHY supporting CDAUI8, CDAUI4 electrical interfaces for QSFP-DD & OSFP optical modules
  • Supports MACSec in applications from 10G to 400G
  • Support MACSec in both 400G retiming & 400G<->100G (reverse gearbox) applications
  • IEEE 802.1AE 256-bit MACSec supporting data rates from 10G to 400G
  • IEEE 1588 supporting up to Class-C to meet stringent 5G timing requirements
  • Proven interoperability with Broadcom switch ASICs and ASSPs using 28-Gbaud PAM-4 and NRZ SerDes
  • Pin-compatible to Broadcom’s standard 400G reverse gearbox and retimer devices for easy upgrade
  • Low power 16nm CMOS technology 


“Data privacy and security have become critical in the data center and cloud infrastructure given the increasing number of security breaches. As cloud and service providers transition their networks to 400G Ethernet to support the growing demand for higher bandwidth and emerging 5G services, it’s imperative that their 400G networks be equipped with 400G MACSec to protect against intrusion attacks, wiretapping and other threats,” said Lorenzo Longo, senior vice president and general manager of the Physical Layer Products Division at Broadcom. “Expanding upon Broadcom’s industry-leading 400G PAM-4 PHY portfolio, the BCM81343 is the first commercial 400G MACSec PHY that delivers up to 800G of switch bandwidth with PTP time-stamping for 5G applications.”

Mellanox adds SONiC to its Spectrum switches

Mellanox Technologies announced ASIC-to-Protocol (A2P) customer support solutions for the SONiC Network Operating System (NOS) on Mellanox Spectrum switches.

SONiC (Software for Open Networking in the Cloud) is a fully open-sourced NOS for Ethernet switches, first created by Microsoft to run Microsoft Azure and now a community project under the Open Compute Project (OCP). SONiC is built on the Switch Abstraction Interface API (SAI) and breaks down traditional monolithic switch software into agile, microservices-based containerized components. This model accelerates innovation within the NOS and the data center by breaking vendor lock-in and simplifying switch programmability, allowing network operators to choose the best-of-breed switching platforms. SONiC offers a full suite of network functionality—like BGP, ECMP, VXLAN, IPv6, and RDMA—that has been deployed and production-hardened in some of the largest data centers in the world.

Mellanox has been a major contributor to SONiC. Mellanox is now adding SONiC support for customers running large deployments of the SONiC NOS on Mellanox SN2000 and SN3000 switches.

“SONiC is an amazingly versatile and scalable NOS for the data center, and Open Ethernet is an incredibly powerful concept,” said Amit Katz, Vice President of Ethernet Switches, Mellanox Technologies. “Every week we hear from more customers who want to combine the power of SONiC with the best-in-class switch silicon in Mellanox Spectrum. Our unique support offering and vast SONiC experience make this easy for new and existing SONiC customers.”

Yousef Kahlidi, Corporate Vice President, Azure Networking at Microsoft Corp. said, “SONiC delivers scalable and efficient cloud networking that offers one optimized NOS that runs on a variety of best-of-breed switches. Offering support for SONiC on their switches allows Mellanox to bring the benefits of SONiC to a larger customer segment.”



Michael Kagan, CTO and co-founder of Mellanox Technologies, talks about the next step for SmartNICs and the company's newly released ConnectX-6 Dx product driven by its own silicon.

Rambus tapes out its 112G XSR SerDes PHY

Rambus taped out its 112G XSR SerDes PHY on a leading-edge 7nm process node optimized for PPA to support data center, networking, HPC, AI and ML applications.

Rambus said its 112G XSR SerDes PHY represents the latest advancement in high-speed signaling technology for die-to-die (D2D) and die-to-optical engine (D2OE) connections.

"As semiconductor markets turn towards chiplets to enable their high-performance products, chip-to-chip interconnects will be critical for maintaining high speed and signal integrity across variable physical distances," said Shane Rau, research vice president, computing semiconductors at IDC. "SerDes PHYs at advanced process nodes, like the 7nm 112G XSR, enable that speed and signal integrity."

“Our 112G XSR SerDes PHY is implemented in the leading-edge 7nm process technology, providing chip and system architects the most advanced platform for their designs,” said Hemant Dhulla, vice president and general manager of IP cores at Rambus. “We are excited to continue our tradition of delivering leading-edge IP solutions that address the systems design challenges of the most demanding applications in networking, HPC and AI.”

The Rambus 112G XSR SerDes PHY includes:

  • High-bandwidth connectivity greater than 800 Gbps per millimeter of beachfront making it ideal for D2D and D2OE interconnects in networking and HPC applications
  • Designed to provide a low-power, high-speed interface that supports chip disaggregation
  • Best-in-class architecture for power, performance, area (PPA) with approximately 1 pJ/bit or 1mW/Gbps power
  • Compliance with Open Interface Forum Common Electrical I/O Consortium (OIF-CEI) standard


Broadband Forum updates Connect Home specs

Broadband Forum has released the latest version of its Connected Home standard User Services Platform (USP) alongside new Wi-Fi data models as part of TR-181.

USP 1.1 enables new deployments to implement quickly into existing infrastructure via support of MQTT, a commonly used protocol in many different aspects of the Connected Home.

The Broadband Forum said its new release also provides northbound REST APIs, which define a standard way of communicating with USP controllers to efficiently manage USP Agents and connected devices integrated with USP. The first version of the Compliance Test Plan is also given in USP 1.1, paving the way for more interoperable solutions in the future by ensuring quality USP implementations.

At the same time, Broadband Forum has published the TR-181 2.13 device data models which defines data models for all types of TR-069 and USP-enabled devices, including end-user devices, Wi-Fi access points, residential gateways, and other network infrastructure devices. This standard incorporates the Wi-Fi Alliance’s Data Elements specification to provide standards-compliant means to periodically retrieve data from USP devices via USP controllers and provide support for real-time control of Internet of Things (IoT) devices through a standardized model of controls and sensors.

The TR-181 data models also provide support for home networks with Multi-AP deployments and the latest Wi-Fi standards, 802.11ax and WPA3. This avoids the need for proprietary data models to be developed by different vendors, unifying Wi-Fi management for all types of deployments.

“The number of connected smart home devices is expected to overtake smartphones by 2021 and this represents a lucrative opportunity for operators,” said Geoff Burke, Chief Marketing Officer at Broadband Forum. “For this opportunity to be realized, standards, which were incredibly important in the mass deployment of broadband networks, are vital for creating a stable ecosystem for Connected Home implementations at scale. These latest updates aim to bring exactly that, positioning USP as the standardized, open, and interoperable platform for smart home and Wi-Fi management.”

https://www.broadband-forum.org/

Broadband Forum kicks off BNG Disaggregation project

The Broadband Forum is launching a new Broadband Network Gateway (BNG) project to define the architecture and requirements for a disaggregated BNG control plane and user plane which separates the control plane and data plane.

BNG disaggregation is expected to bring benefits such as centralized locations for configuration and IP address management, leading to faster delivery of new services. The work will also ensure the control plane and user plane can be easily scaled according to customer demand.

Intel outlines “Barlow Pass” - 2nd gen Optane DC persistent memory

Intel outlined a series of milestones in advancing memory and storage for cloud, artificial intelligence and network edge applications.

Developments include:

  • Intel plans to operate a new Optane technology development line at its facilities in Rio Rancho, New Mexico; 
  • The second-generation of Intel Optane DC Persistent Memory, code-named “Barlow Pass,” scheduled for release in 2020 with Intel’s next-generation Intel Xeon® Scalable processor 
  • Intel’s industry-first demonstration of 144-layer QLC (Quad Level Cell) NAND for data center SSDs (solid-state drives), which are also expected in 2020.


Intel said the combination of its Optane technology with QLC 3D NAND technology on a single M.2 module enables Intel Optane memory expansion into thin and light notebooks and certain space-constrained desktop form factors – such as all-in-one PCs and mini PCs. The new product also offers a higher level of performance not met by traditional Triple Level Cell (TLC) 3D NAND SSDs today and eliminates the need for a secondary storage device.

Aryaka extends SD-WAN with HybridWAN capability

Aryaka has extended its Global Managed SD-WAN with a HybridWAN capability, where a combination of Aryaka’s Layer 2 core connectivity and Aryaka-managed internet connectivity will provide a more flexible experience.

The Aryaka core option offers guaranteed performance for business-critical traffic, while the Internet option offers cost-effective transport for non-priority traffic, an ‘Internet-first’ paradigm for enterprise connectivity that tracks the ‘cloud-first’ paradigm for applications. This also helps enterprises consolidate their branch appliances resulting in a lower TCO.

Aryaka said its HybridWAN is combined with two additional innovations to help secure SD-WAN adoption; zone-based firewall capabilities and micro-segmentation in support of multi-tenancy.

The Aryaka service integrates edge intelligence, security, application optimization and visibility. Zones extend Aryaka’s existing north-south access firewall to east-west, such as separating employee, DMZ and external LANs. Micro-segmentation then extends this partitioning, either within a single enterprise or as part of a multi-tenant branch, across the SD-WAN.

“Aryaka has been at the forefront of these two trends, offering the first truly global managed SD-WAN Service,” said Shashi Kiran, CMO of Aryaka. “We’re now enhancing this even further with additional flexibility and choice, but not at the expense of added complexity, such as when an enterprise must manage different WAN providers and technologies or a traditional MPLS service where direct cloud connectivity takes extra effort.”

https://www.aryaka.com/

Bigleaf raises $21 million for its SD-WAN

Bigleaf Networks, a start-up based in Beaverton, Oregon, announced $21 million in Series B funding for its cloud-first SD-WAN.

Bigleaf says that while current networking technologies have been built for the large enterprise use-case of site-to-site networking, there is a gap for SMB and mid-sized companies seeking SD-WAN solutions.

Bigleaf is exclusively focused on partner-led channels, including telecom operators.

The funding round was led by Updata Partners with participation from the Oregon Venture Fund, SeaChange Fund, and other existing investors.

https://www.bigleaf.net

Ericsson makes US$1.23 billion provision for U.S. investigation

Ericsson made a provision of SEK 12 billion (US$1.23 billion) to resolve the ongoing investigation by U.S. authorities. The process to find a resolution is still ongoing, but Ericsson reckons it may face a monetary sanction of US$1 billion.

As previously disclosed, Ericsson has been co-operating voluntarily since 2013 with an investigation by the United States Securities and Exchange Commission (SEC) and, since 2015, with an investigation by the United States Department of Justice (DOJ) into Ericsson’s compliance with the U.S. Foreign Corrupt Practices Act (FCPA) and the process is still ongoing. The investigation covers a period ending Q1 2017 and revealed breaches of the Company’s Code of Business Ethics and the FCPA in six countries: China, Djibouti, Indonesia, Kuwait, Saudi Arabia and Vietnam.

The company previously communicated that the resolution of the investigations will result in material financial and other measures. While Ericsson cannot comment in detail on the ongoing process with the U.S. authorities, the Company can with current visibility now estimate the cost and thus make a provision, which will impact the third quarter 2019 results by SEK 12 b. The provision constitutes the Company’s current estimate of expenditure related to resolving the U.S. investigations, of which the combined monetary sanctions from SEC and DOJ is estimated at USD 1 b., and the remainder pertains to other costs related to resolving the investigation. The provision will be booked as Other Operating Expenses in the income statement of Segment Emerging Business and Other.

Börje Ekholm, President and CEO, says: ”Over the last two years we have operationally turned around our company and established a strong portfolio and competitive cost structure. With today’s announcement we confront another legacy issue and take the next step in resolving it. We have to recognize that the Company has failed in the past and I can assure you that we work hard every day to build a stronger Ericsson, where ethics and compliance are cornerstones in how we conduct business. Over the past two years, we have made significant investments in our ethics and compliance program including our investigative capabilities and have taken actions against employees who have transgressed our values and standards.”

HPE completes acquisition of Cray

Hewlett Packard Enterprise completed its previously announced acquisition of Cray Inc., the legendary supercomputer developer. The deal, which was first announced in May, was valued at approximately $1.3 billion, net of cash.

“Bringing together Cray and HPE establishes the most comprehensive end-to-end portfolio across compute, storage, software and services in the fast-growing high performance computing and artificial intelligence market segments,” said Phil Davis, president, Hybrid IT, Hewlett Packard Enterprise. “But, the real value is what we can accomplish together as one team. We are united in our vision to be a global leader in high performance computing. By combining the teams’ deep expertise and R&D engines, we are better positioned to help our customers solve their most data-intensive challenges both today and well into the future.”


Cray traces its origin back to 1972 and the founding of Cray Research. The company is currently based in Seattle, with US-based manufacturing, and approximately 1,300 employees worldwide. The company delivered revenue of $456 million in its most recent fiscal year, up 16 percent year over year.

Cray recently announced an Exascale supercomputer contract for over $600 million for the U.S. Department of Energy’s Oak Ridge National Laboratory. The system, which is targeted to be the world’s fastest system, uses Cray’s new Shasta system architecture and Slingshot interconnect. The company was also part of an award with Intel for the first U.S. Exascale contract from the U.S. Department of Energy’s Argonne National Laboratory, with Cray’s portion of the contract valued at over $100 million.

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