Tuesday, September 24, 2019

Innovium debuts smaller Ethernet switching chip

Innovium introduced a smaller Ethernet switch chip family for designs ranging from 1.2 to 6.4Tbps.

The new TERALYNX 5, which is expected to begin sampling in Q4 2019, is aimed at ToR, enterprise, edge, and 5G applications. Key capabilities include up to 128x NRZ/PAM4 SERDES, 10GbE to 400GbE ports, the largest on-chip buffers, powerful analytics, and leading performance per $ and performance per watt.


“The Innovium team has amassed a breakthrough, innovative IP portfolio, designed from the ground up, enabling us to deliver a programmable, low-latency 12.8T switch in production a full technology node earlier,” said Rajiv Khemani, CEO and Co-Founder of Innovium Inc. “We are delighted to further optimize these technologies for ToR and edge applications with TERALYNX 5, allowing a single consistent architecture to power data center switching applications from top to bottom with unmatched performance and value.”

TERALYNX 5 Family Highlights:

  • Wide range of pin-compatible SKU options: 1.2Tbps, 2.4Tbps, 3.2Tbps, 4.8Tbps, 6.4Tbps
  • Up to 128 SERDES PAM4 or NRZ SERDES enabling port speeds from 10Gbps to 400Gbps
  • Largest on-chip buffer for switch in this class (45MB+)
  • Leading L2, L3 table sizes and ACL’s
  • Robust RoCE and PFC support for lowest latency and rich QoS necessary for distributed storage and AI applications
  • IEEE 1588 v2 timing synchronization required in 5G and other data center infrastructure
  • FLASHLIGHT v2 line-rate HW analytics with unprecedented microburst detection features and application correlation
  • Up to 2x performance per $ and performance per watt vs. alternatives
  • SW programmability for support of new protocols, achieved without impact to throughput or latency suffered by alternatives
  • Fully SW and architecture compatibility with TERALYNX 7, scaling solutions to 12.8Tbps


See also