Thursday, April 6, 2017

Open-Silicon unveils Interlaken Chip-to-Chip Interface Supporting 1.2 Tbit/s

Open-Silicon, a supplier of system-optimised ASIC solutions and founding member of the Interlaken Alliance, announced the release of its eighth-generation Interlaken IP core, providing support for up to 1.2 Tbit/s bandwidth and up to 56 Gbit/s SerDes rates with forward error correction (FEC).

Open-Silicon's high-speed ch

ip-to-chip interface IP is based on an architecture that is designed to be flexible, configurable and scalable, making it suitable for high-bandwidth networking applications such as routers, switches, framer/MAC, OTN switch, packet processors, traffic managers, look aside processors/memories, data centre and other high-end networking and data processing systems.

Open Silicon's latest 8th generation Interlaken IP core specifically delivers:

1. Support for bandwidth of up to 1.2 Tbit/s and up to 56 Gbit/s SerDes data rates.

2. Improved flexibility via the ability of a single instance of the core to have multiple configurations, for example, a single 1.2 Tbit/s interface or four 300 Gbit/s interfaces, selectable at power-up.

3. Multiple user-data interface options, including 128 bit or 256 bit wide with one, two, four or eight segments.

4. SerDes width support for 8, 10, 16, 20, 32, 64 and 80-bits.

Open-Silicon's 8th generation Interlaken IP is available immediately.

See also