Saturday, October 10, 2015

Altera Demos FPGAs for CCAP Architecture

Altera demonstrated its new, flexible and upgradeable silicon solution for  multi-service operators (MSOs) adopting distributed CCAP (converged cable access platform) architecture.

The Altera DOCSIS Remote (MAC) PHY design, which is being demonstrated with partners Analog Devices, and Capacicom, enables cable operators to more efficiently and cost-effectively meet the ever-increasing need to segment cable networks, driven by the demand of high-speed Internet, unicast 4K video and other multimedia content.

The solution uses Altera Arria 10 FPGAs and Analog Devices' class-leading digital-to-analog converters (DACs) and analog-to-digital converters (ADCs), combined with Capacicom's MAC and PHY implementation, resulting in state-of-the-art radio frequency (RF) performance.

"With today's Altera FPGA portfolio and onward technology roadmap coupled with Capacicom's substantial experience in DOCSIS PHY and MAC layers, ADI has now found the perfect combination of partners to extend its leadership in high-performance analog into cable infrastructure solutions," said Carlton Lane, Analog Devices cable solutions manager. "ADI, Altera and Capacicom have set up a long-term collaboration to create the semiconductor industry reference platform for R - (MAC) PHY, with a continuing roadmap commitment to the lowest power consumption and cost per port."

Arria 10 FPGAs and SoCs deliver the highest performance at 20 nm.  The company said its Arria 10 FPGAs and SoCs are up to 40 percent lower power than previous generation FPGAs and SoCs and feature the industry's only hard floating-point digital signal processing (DSP) blocks with speeds up to 1,500 giga floating-point operations per second (GFLOPS).

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