Monday, August 19, 2013

Marvell's New Prestera Switching Processors Target Dynamic Access/Aggregation

Marvell introduced its Prestera DX4200 series of packet processors for the access and aggregation layers of fixed and mobile networks.

The new product family, which represents the eight generation of Marvell switching silicon, is implemented in 28nm. The design integrages multi-core ARM v7 CPUs, a carrier grade traffic manager and a flexible IPv6 packet processing pipeline to enable dynamic software defined networking and advanced service virtualization.

It supports CAPWAP, MPLS, VPLS, OAM, SPB and Bridge Port Extension, and offer synchronization features. An integrated InterLaken interface also enables the development of transport and circuit switched solutions while leveraging the service enabling paradigms of the DX4200. The integrated traffic manager offers hierarchical flow based quality of service and massive external buffering enabling tens of thousands of applications and users through unique queuing schemes that insure no variance in user experience across different access models. Sampling begins in September.

"As demand for higher service density per watt increases, Marvell is uniquely positioned to offer platforms for the software defined storage, networking, mobile and compute clouds being designed today," said Ramesh Sivakolundu, vice president for the Connectivity, Services and Infrastructure Business Unit (CSIBU) at Marvell Semiconductor.