Monday, June 3, 2013

Tabula Releases 100GE Packet Parser

Tabula, a start-up based in Santa Clara, California, announced the availability of the latest addition to its suite of high-performance packet processing solutions: the 100G Ethernet Packet Parser Reference Design Kit. This latest kit is based on its new ABAX2P1 3PLD and supported by its Stylus revision 2.6.2 compiler.

The 100 GbE packet parser includes the following features:
  • 149M packets/sec at the minimum packet size of 64 bytes
  • 100 GbE stream support at 100% efficiency
  • Deterministic latency of 17 ns
  • Guaranteed bandwidth of 122 Gbps
  • Less than 1.5 Watts per 100 GbE stream

Earlier this year, Tabula unveiled  its suite of high-performance packet processing solutions aimed at 100G applications.

The technology focuses on routing of high-performance buses, on-chip RAM throughput, and timing closure for the ultra-high-performance functions required by 100G systems. Tabula will also leverage Intel's 22nm Tri-Gate technology.

The packet processing solutions, combined with Tabula’s new ABAX2P1 3PLD, deliver processing of four 100G streams on a single chip, a search engine capable of supporting 100G packet traffic, and a 12x10G-to-100G bridge.

The company said its solution leverages innovations four key areas: Programmable 3D architecture, RTL compiler, leading-edge process technology using Intel's 22nm Tri-Gate technology, and 3PLD devices.

In 2011, Tabula announced $108 million in Series D funding for its 3PLD ABAX programmable logic products.