Tuesday, November 29, 2011

TI Scales its Keystone Processors for Cloud RANs

Texas Instruments is scaling its KeyStone multicore processor architecture for cloud RANs, which promise immense pools of processing capacity for use by clusters or power-efficient base stations.

KeyStone is Texas Instruments' multicore infrastructure architecture for base stations. The new KeyStone enhancements for C-RAN include expanding Multicore Navigator's Queue Manager to provide over 16K queues and one million descriptors. In addition, TI's Hyperlink chip-to-chip interface is expanded to 100Gbps with dual-port operation and its integral wire-rate Ethernet switch is upgraded to 10Gbps per port.

The company said these enhancements allow a larger pool of TI's KeyStone-based System-on-Chips (SoC) to interconnect and function as a single SoC, a critical capability for C-RAN base stations requiring large scale processing from baseband IQ through Ethernet IP.

"By leveraging the scalability of the KeyStone architecture, we have provided enhancements that represent a quantum leap in multicore processing performance," said Tom Flanagan, director of technical strategy, wireless base station infrastructure, TI. "With KeyStone, we can now create device pools with unheard of levels of capacity -- nearly 800 cores pooled to appear as a single multicore device. That's the power of KeyStone, a true multicore platform and differentiator, when it comes to choosing a silicon partner for C-RAN applications." http://www.ti.com

  • In June 2011, Texas Instruments has extended its base station silicon architecture with two new chips designed for small cell applications. With this introduction, TI's base station portfolio now scales from enterprise femto cells, to neighborhood pico cells, to high capacity metro cells -- all leveraging the same "Keystone" multicore architecture and common software libraries. These scalable SoCs encompass a mix of processing elements including radio accelerators, network and security coprocessors, combined fixed-and floating-point digital signal processors (DSPs) and an ARM RISC processor, providing the ideal foundation for layers 1, 2 and 3 and transport processing for high performance small cell base stations.

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