Sunday, June 19, 2011

TI Extends its Base Station Architecture for Metro, Pico and Femtos

Texas Instruments has extended its base station silicon architecture with two new chips designed for small cell applications. With this introduction, TI's base station portfolio now scales from enterprise femto cells, to neighborhood pico cells, to high capacity metro cells -- all leveraging the same "Keystone" multicore architecture and common software libraries. These scalable SoCs encompass a mix of processing elements including radio accelerators, network and security coprocessors, combined fixed-and floating-point digital signal processors (DSPs) and an ARM RISC processor, providing the ideal foundation for layers 1, 2 and 3 and transport processing for high performance small cell base stations.

As the mobile market continues to grow, the underlying infrastructure is experiencing greater pressures associated with form factor, performance and power consumption," said Ian Drew, executive vice president of marketing, ARM. "Texas Instruments' use of the ARM Cortex-A8 provides new levels of energy efficiency and higher performance to the small cell base station market."

The TCI6612 and TCI6614's processing elements include two or four TMS320C66x fixed- and floating-point DSP cores, as well as a power efficient ARM Cortex™-A8 RISC processor. The ARM core is typically used for control plane processing. The remaining base station functions, including all baseband and packet processing, are handled by the DSP cores coupled with configurable wireless, network and security coprocessors.

The devices are code compatible with TI's entire KeyStone multicore portfolio, as well the TMS320C64x DSP generation, ensuring all previous software investments made by TI customers can be reused. Sampling is expected in Q3.

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