Sunday, June 19, 2011

NSN Invests in ClariPhy for 10/40/100G Advanced Signal Processing

Nokia Siemens Networks has invested an undisclosed amount for a stake in ClariPhy, a start-up based in Los Altos, California and Cordoba, Argentina. ClariPhy provides advanced integrated circuits that improve the efficiency and capacity of networks used for transporting vast quantities of information.

Specifically, Nokia Siemens Networks' investment supports ClariPhy's development of highly integrated single chip complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) for high performance optical networks digital signaling processing (DSP). Essentially, these semiconductor chips integrate the multiple tasks required by transport networks such as conversion of analog signals from optical sensors to digital, digital manipulation, and back to analog form again, faster and more efficiently.

"The rapid processing of digital signals is crucial in high capacity optical networks," said Vesa Tykkyläinen, head of the optical networks business line at Nokia Siemens Networks. "We are investing in a company that is innovative and a forerunner of the coherent chip technology*** with 40nm (nanometer) CMOS for 40G. ClariPhy will also be among the firsts to use 28nm CMOS for 100G, high-gain and low-latency soft-decision****, forward error correction and many other innovations. Together with our leading R&D, ClariPhy will enable us to be at the forefront of high performance and low power consumption next-generation optical platforms capable of 400G and beyond along with reducing equipment footprint".http://www.clariphy.comClariPhy's portfolio includes mixed-signal integrated circuits (ICs) for 10, 40 and 100 Gbps optical networking and communication applications. The new class of single chip MXSP ICs that significantly increase an optical network's reach and tolerance to impairments (such as chromatic dispersion, polarization mode dispersion and fiber nonlinearity). The company's line of 10G, 40G and 100G networking chips are based on advanced MXSP schemes such as Maximum Likelihood Sequence Estimation (MLSE) and Coherent Detection that approach the limits of achievable performance. ClariPhy's implementation of these schemes in 40 nm single-chip CMOS enables equipment designers to reduce cost and power by integrating multiple system functions into customized System on Chip (SoC) solutions.

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