Monday, April 4, 2011

Vitesse and AppliedMicro Collaborate on 40G/100G Enhanced FEC

Vitesse Semiconductor and AppliedMicro announced an alliance to drive a standard approach for 40G and 100G Enhanced Forward Error Correction (eFEC) technology. The collaboration allows AppliedMicro to license Vitesse's patented portfolio of 40G and 100G hard decision eFEC cores for its FPGA and ASSP solutions aimed at emerging Optical Transport Network (OTN) applications requiring best-in-class net electrical coding gain (NECG) with the lowest implementation complexity and cost. The two companies will mutually cross license three OTN applications including AppliedMicro's 10GE LAN Signal Mapping to OTU2 Signal patent and Vitesse's Continuously Interleaved Error Correction patent.

Forward Error Correction is widely used in fiber optic communications to reduce bit error rate in typically noisy signal environments. As metro and long-haul networks transition from 10G to 40G, and up to 100G high speed data rates, the challenges in developing cost-effective, improved signal-to-noise ratio solutions become more substantial.

"Providing the industry a standardized eFEC approach for emerging OTN solutions in metro and long-haul networks is our ultimate goal," said Steve Perna, vice president of product marketing at Vitesse. "This effort provides significant technology advancements and value to customers who need an effective and reliable way to transmit data, voice, and video at faster rates in OTN applications. As networks migrate and Ethernet becomes the ubiquitous protocol, this capability will be increasingly critical."

"We are pleased to work with Vitesse to drive a standard eFEC approach for 40G and 100G data rates," said George Jones, vice president of marketing and business development at AppliedMicro. "The combination of AppliedMicro and Vitesse supporting this family of eFEC cores in the marketplace addresses the challenges of time-to-market and interoperability. AppliedMicro's roadmap of SoftSilicon® solutions enables immediate implementation of these eFEC cores for customer designs. Our complementary ASSP solutions will utilize the same cores and provide both software and hardware investment protection for our customers."