Monday, March 16, 2009

ClariPhy Launches Single-Chip CMOS CDR for 10 Gbps Impairments

ClariPhy Communications, a fabless semiconductor company specializing in high speed communications ICs, introduced its 10 Gbps clock and data recovery (CDR) integrated circuit (IC) with maximum likelihood sequence estimation (MLSE). The all-digital single-chip CMOS IC provides electronic dispersion compensation (EDC) of impairments inherent to optical fiber.

ClariPhy said MLSE (also referred to as maximum likelihood sequence detection or MLSD) is known to be the theoretically optimal EDC architecture, which evaluates a sequence of received data samples to determine the most likely correct transmitted sequence. MLSE is used ubiquitously in lower speed communications applications such as hard disk drives and voice band modems, but only ClariPhy has delivered MLSE at 10 Gbps data rates in CMOS, thereby achieving maximum performance while leveraging CMOS cost and power trends following Moore's Law.

ClariPhy design provides significantly greater tolerance to chromatic dispersion (CD), polarization mode dispersion (PMD) and nonlinear distortion, impairments that are prevalent in telecom networks. Furthermore, at less than two watts, the power dissipation of the single-chip CMOS CL1012 is lower than alternative multi-chip implementations of MLSE utilizing silicon germanium process technology.

The CL1012 CDR with MLSE is manufactured in a 65 nm CMOS process and assembled in a 10×10 mm2 flip chip BGA package.

ClariPhy is headquartered in Irvine, CA, and has an office in Silicon Valley and a design center in Cordoba, Argentina. ClariPhy's investors include Norwest Venture Partners, Onset Ventures, Allegis Capital and Pacific General Ventures.