Monday, October 15, 2007

Octasic Announces Clock-less DSP Core Architecture

Octasic announced its Opus DSP architecture promising greater processing power and lower power consumption.

Whereas other new DSP architectures deliver better power efficiency but break the traditional programming model, Octasic said its new asynchronous Opus architecture maintains a traditional programming model preserving customers' investment in applications and skill set. The ability to achieve 3 times more performance per watt than current designs enables developers to leverage a multi-core DSP architecture without re-writing code. The Opus kernel and Integrated Development Environment (IDE) provide tools to help develop, test, and debug software.

"While the DSP core construction is clock-less, to the programmer it presents a traditional processing model. This is important to allow today's DSP programmers to take full advantage of its capabilities without having to be retrained to re-write and re-partition existing applications," said Doug Morrissey, Octasic CTO.

Octasic's new Vocallo multi-core media gateway DSP is the first Octasic product based on the Opus core.

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