Sunday, December 17, 2006

OIF Finalizes Scalable System Packet Interface

The Optical Internetworking Forum (OIF) has finalized the Scalable System Packet Interface (SPI-S) implementation agreement.

SPI-S is a channelized, streaming-packet interface that scales from 6 Gbps to hundreds of Gbps for chip-to-chip and backplane applications. It is a successor to the widely deployed OIF SPI 4.2 interface, and leverages the OIF's Common Electrical Interface (CEI) to take advantage of high rate serial physical interconnects.

SPI-S is specified to run over CEI, which is defined at 6 and 11 Gbps for both short reach and long reach applications. SPI-S can also be used with other physical interconnects including OIF's SxI-5. The OIF also recently announced the initiation of a CEI-25 project to extend the CEI serial interface into the 25 Gbps range. The scalable nature of SPI-S will allow it to take advantage of CEI-25 when the next generation interconnect is fully defined.

SPI-S uses either industry-standard 64B66B framing or optionally, the enhanced OIF CEI Protocol (CEI-P) framing that provides Forward Error Correction (FEC) support, yet retains a 64/66 clock ratio. FEC is likely to be useful when 11 Gbps PHYs are used in backplane applications and when future, higher speed PHYs are employed.

SPI-S also retains the high-availability focus of the SPI family of interfaces. Like those other protocols, SPI-S is defined to be self-recovering from a catastrophic event on its interface such as a protective switchover of a card.

"The OIF's existing System Packet Interface SPI 4.2 is the most widely deployed chip-to-chip streaming interconnect for high speed data paths," said Dave Stauffer, of IBM and chair for the OIF's Physical and Link Layer Working Group. "Given the highly scalable nature of the new SPI-S, it should have legs to stand for a decade or more as the industry's next definitive streaming-packet interface. The speed and number of bit lanes employed by SPI-S can be directly scaled to very high rates."