Thursday, July 13, 2006

Avago Demonstrates 12.5 Gbps SerDes Core in 65 Nm CMOS

Avago Technologies, the privately held semiconductor company that spun out of Agilent Technologies, has validated its SerDes core in 65 nm CMOS process technology. This milestone advances the state of SerDes (Serialization/Deserialization) ASIC core design from today's mainstream 90 nm to 65 nm process technology.

Avago said its embedded SerDes intellectual property (IP) core offers extremely low jitter, making it possible to integrate as many SerDes channels as needed onto a single 65-nm CMOS (complementary metal oxide semiconductor) chip, each operating at up to 12.5 Gbps. Additionally, the new SerDes core features Avago's proprietary clockless Decision Feedback Equalization, on-chip BERT for channel bit error rate optimization, LC-based oscillator for improved power-supply noise rejection, and 1149.6 AC-Extest for testing AC-coupled connections.

Avago has shipped over 25 million embedded SerDes channels to date to manufactures of networking, computing and storage hardware products.

"This technology advancement, representing our fifth generation SerDes core, will continue to provide networking and computing OEMs with competitive advantages," said James Stewart, vice president and general manager of Avago Technologies' Enterprise ASIC division.

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