Monday, November 29, 2004

Zarlink Offers Digital Timing Chip for SONET/SDH Line Cards

Zarlink Semiconductor introduced a DPLL (digital phase locked loop) for optical line cards operating at rates up to OC-3/STM-1. The DPLL device addresses dense line card "real estate" constraints and may be used in combination with Zarlink's family of analog PLLs to provide an end-to-end timing and synchronization solution for higher-speed SONET/SDH networking equipment.


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