Showing posts with label Xilinx. Show all posts
Showing posts with label Xilinx. Show all posts

Tuesday, September 12, 2017

Huawei picks Xilinx FPGAs for Accelerated Cloud Server

Huawei has selected Xilinx Virtex UltraScale+ FPGAs to power their first FP1 instance as part of a new accelerated cloud service. The Huawei FPGA Accelerated Cloud Server (FACS) is a platform that enables users to develop, deploy and publish new FPGA-based services and applications on Huawei Public Cloud.

Xilinx said its FPGAs can provide a 10-50x speed-up for compute intensive cloud applications such as machine learning, data analytics, and video processing.  Xilinx FPGAs can be reconfigured in less than a second to a different design that is hardware optimized for its next workload.

"The Huawei FACS is a fully integrated hardware and software platform offering developer-to-deployment support with best-in-class industry tool chains and access to Huawei's significant FPGA engineering expertise," said Steve Langridge, Director, Central Hardware Institute, Huawei Canada Research Center.

The FPGA Accelerated Cloud Server now available on the Huawei Public Cloud.

http://www.hwclouds.com/product/fcs.html
http://www.huaweicloud.com

Monday, July 10, 2017

Baidu deploys Xilinx FPGAs for cloud acceleration

Xilinx announced that Baidu has deployed Xilinx FPGA-based application acceleration services into its public cloud, specifically for the Baidu FPGA Cloud Server, a new service that leverages Xilinx Kintex FPGAs, tools and the software required for hardware-accelerated data centre applications such as machine learning and data security.

The Baidu FPGA Cloud Server provides a complete FPGA-based hardware and software development environment, including hardware and software design examples, and is designed to help users quickly develop and migrate applications with reduced development costs.

The Baidu service is based on each FPGA instance serving as a dedicated acceleration platform that is not shared between instances or users. The design examples provided services including cover deep learning acceleration, encryption and decryption.

Xilinx claims that FPGA-enabled servers can deliver a 10x to 80x performance per watt advantage compared to CPU-only servers. In addition, as they are dynamically reconfigurable, Xilinx FPGAs can support a range of workloads, including machine learning, data analytics, security and video processing.



  • Separately, Baidu announced a partnership with Microsoft for its new open source autonomous driving platform, Apollo. Baidu unveiled Apollo in April, featuring cloud services, software and reference hardware/vehicle platforms, and expects the technology will be running on roads by late 2020.
  • In addition, Conexant, a provider of audio and voice technology solutions, announced it was collaborating with Baidu to release development kits and reference designs for device makers to develop far-field voice-enabled artificial intelligent (AI) devices running on Baidu's DuerOS platform. The development kits and reference designs will feature Conexant's CX20924 4-microphone and CX20921 2-microphone voice input processing solutions and DuerOS, a conversation-based AI system that enables access to a voice-activated digital assistant for mobile phones, TVs and other devices.

Friday, March 17, 2017

Xilinx to Demo FPGAs in 400G Ethernet, FlexE

At this week's Optical Fiber Communications (OFC) Conference and Exhibition in Los Angeles Xilinx will debut a number of solutions for high speed data center interconnect (DCI) solutions.

Xilinx will participate in a 400GE multi-vendor network demo featuring the world's first standards-based 400GE MAC and PCS IP in a Xilinx Virtex UltraScale+™ VU9P FPGA. Showcasing the emerging 400GE standard interoperability between multiple vendors, the demo illustrates the Xilinx 400G solution connecting to a Finisar 400GE CFP8 module which in turn connects to a Spirent 400G test module in the Ethernet Alliance booth.

Xilinx will also showcase a complete FlexE 1.0 solution with bonding, sub-rating and channelization on its UltraScale+ FPGAs. This solution demonstrates how multiple clients can be transported using FlexE and highlights the ability of FlexE to carry larger data pipes and match them to transport links for optimal utilization of the link budget. This solution allows network operators to maximize optical performance and lower operating costs over existing infrastructure.

A third demo shows how LLDP packets can be snooped on transport line cards to allow a SDN controller to build a network topology for automation integral to data center networks. It also shows the use of IEEE compliant MACsec to encrypt and authenticate the link for security. As more and more critical applications and data migrate to the cloud, MACsec provides data encryption and authentication to preserve privacy. Such a solution is mandatory in front of a traditional DSP to provide a complete DCI solution.

Another demonstration showcases Xilinx's new 56G PAM-4 transceiver test chip in 16nm FinFET delivering optimized performance for backplane and LR applications.

http://www.xilinx.com

Friday, February 24, 2017

Xilinx Integrates RF analogue Tech into All Programmable MPSoCs

Xilinx has announced what it claims is a disruptive integration and architectural technique for 5G wireless with the addition of RF-class analogue technology into its 16 nm All Programmable MPSoC products.

Xilinx's new All Programmable RFSoCs eliminate the need for discrete data converters, providing a claimed 50-75% reduction in terms of power and footprint for 5G massive MIMO and millimetre-wave (mmWave) wireless backhaul applications.

The company noted that large scale 2D antenna arrays will be a key element for increasing spectral efficiency and network densification for 5G networks. The integration of ADCs and DACs into Xilinx's All Programmable SoC devices is designed to enable radio and wireless backhaul units to meet previously unattainable power and form factor demands, while also allowing higher channel density.

In addition, the new RFSoC devices can also help manufacturers streamline design and development cycles and meet 5G deployment timelines.

Xilinx's new All Programmable RFSoC devices offer features including:

1. Direct RF sampling to simplify analogue design and enhance accuracy and enable a smaller form factor and lower power consumption.

2. 12-bit ADCs supporting up to 4 GS/s, high channel count, with digital down-conversion.

3. 14-bit DACs supporting up to 6.4 GS/s, high channel count and digital up conversion.

The new RFSoC integrated subsystem specifically targets a range of applications including high bandwidth remote radio and backhaul systems for 5G deployments and remote node architectures (R-PHY) for DOCSIS 3.1 cable broadband systems.


Monday, May 23, 2016

Xilinx Adds Data Center Accelerators to 16nm UltraScale+ Roadmap

Xilinx plans to add acceleration enhanced technologies for the Data Center to its 16nm UltraScale+ product roadmap.

The resulting products will deliver the combination of Xilinx's 16nm FinFET+ FPGAs with integrated High-Bandwidth Memory (HBM), and support for the recently announced Cache Coherent Interconnect for Acceleration technology (CCIX).

CCIX is initially driven by a group of seven companies to enable an acceleration framework that works with multiple processor architectures.

Specifically, Xilinx HBM-enabled FPGAs will improve acceleration capabilities by offering 10X higher memory bandwidth relative to discrete memory channels. HBM technology enables multi-terabit memory bandwidth integrated in package for the lowest possible latency.

"Having already delivered 19 billion transistors on a chip at 20nm leveraging our second generation 3D IC technology, we are creating a third generation 3D IC breakthrough  for data center acceleration and other compute intensive designs," said Victor Peng, executive vice president and general manager, Programmable Products at Xilinx. "When combined with next generation CCIX acceleration framework and our software defined SDAccel™  development environment, this technology will enable a new breed of high-density, flexible platforms for accelerating compute, storage and networking applications."

http://www.xilinx.com

Saturday, March 12, 2016

Xilinx Develops 56G PAM4 Transceiver Technology

Xilinx has developed a 16nm FinFET+-based programmable device running 56G transceiver technology using the 4-level Pulse Amplitude Modulation (PAM4) transmission scheme.

Xilinx said PAM4 solutions will help drive the next wave of Ethernet deployment for optical and copper interconnects by doubling bandwidth on the existing infrastructure.

"Our customers are already anticipating how to accelerate their next generation applications. We recognize the need to raise awareness of 56G PAM4 technology solutions now, to help prepare them to transition their own designs," said Ken Chang, vice president of the SerDes technology group at Xilinx. "I am delighted to be able to showcase our technology."

http://www.xilinx.com

Friday, February 5, 2016

Xilinx FPGA to Support 25G per Lane Copper Cabling at Five Meters

Xilinx announced that its Virtex UltraScale FPGAs have achieved compliance to the 25GE, 50GE and 100GE copper cable and backplane IEEE and related specifications, which supports up to five meters of copper cabling in the data center and up to one meter of backplane interconnect.

These specifications include the IEEE 802.3bj 100GBASE-CR4/KR4, IEEE 802.3by 25GBASE-CR/CR-S/KR/KR-S, and 25 Gigabit Ethernet Consortium 50GBASE-CR2/KR2. Data center customers can now leverage nx25G lanes of copper cabling versus optics for more cost and power-optimized solutions to connect servers to top-of-rack switches using any off-the-shelf, specification-compliant vendor.

"With Virtex UltraScale FPGAs in volume production, and as the industry's only FPGA supplier compliant to the 25Gb per lane copper cable and backplane specifications, we are committed to helping our customers utilize the lowest risk and most cost effective solutions for their data centers," said Kirk Saban, senior director of FPGA and SoC product management and marketing.

http://press.xilinx.com/2016-02-02-Xilinx-Transceiver-Breakthrough-Brings-Greater-Cost-Efficiency-to-Data-Center-Interconnects

Xilinx Tech Ventures to Invest in Cloud & NFV Start-ups

Xilinx Technology Ventures is launching a Data Center Ecosystem Investment Program that will focus primarily on technologies that expand Xilinx's data center products and offerings and ignite industry innovation, time to market advantage, and lower overall cost of ownership. The new program targets solutions for emerging workload applications such as machine learning, image and video processing, data analytics, storage data base acceleration, and network acceleration.

As part of this program, Xilinx recently completed its first data center ecosystem investment in TeraDeep, Inc., a company specializing in convolutional neural networks-based machine learning. TeraDeep is widely recognized for its state-of-the-art deep learning expertise and acceleration technology which runs on Xilinx® FPGAs. Through this investment, TeraDeep will continue to work closely with Xilinx to further optimize its solutions on Xilinx-based FPGA boards.

"Through this investment program, we want to help enable start-ups that create libraries, middleware, and application software to accelerate the broad deployment of Xilinx FPGA solutions in the Data Center," said Greer Person, senior director, Corporate Business Development. "In addition to funding, our portfolio companies often gain access to Xilinx business and technology experts, products, and design environments to help them create more competitive solutions, accelerate time-to-market, and reduce development costs."

http://www.xilinx.com/about/technology-investments.html

Sunday, January 31, 2016

Xilinx Ships 16nm Virtex UltraScale+ FinFET FPGAs

Xilinx announced first customer shipment of its Virtex UltraScale+ FPGA, the industry's first high-end FinFET FPGA built using TSMC's 16FF+ process.

The Virtex UltraScale+ devices join the Zynq UltraScale+ MPSoCs and Kintex UltraScale+ FPGAs showcasing the availability of all three families of the Xilinx 16nm portfolio. The UltraScale+ portfolio provides 2 – 5x greater system-level performance/watt over 28nm devices and is suited for LTE Advanced and early 5G Wireless, Automotive ADAS, Cloud Computing, Industrial Internet-of-Things (IoT), SDN/NFV, and Video/Vision markets.      

Xilinx said it is actively engaged with more than one hundred customers on the UltraScale+ portfolio with design tools, and has already shipped devices and/or boards to over sixty of these customers.

"The successful delivery of our Virtex UltraScale+ FPGA marks the availability of all three UltraScale+ 16nm families, which are already providing more than one hundred customers with the ability to develop next generation designs using cutting edge FinFET-based devices, development boards and tools. Our "Three-Peat" execution – with three consecutive generations of leadership technology at 28nm, 20nm, and now at 16nm – showcases our sustained commitment to being first to market with the most advanced products in our industry," said Victor Peng, executive vice president and general manager of the Programmable Products Group at Xilinx.

http://www.xilinx.com

Xilinx Outlines its 16nm UltraScale+ Family of FPGAs

Xilinx introduced its next-generation 16nm UltraScale+ family of FPGAs, featuring new memory, 3D-on-3D and multi-processing SoC (MPSoC) technologies.

The UltraScale+ family also includes a new interconnect optimization technology and will leverage TSMC's 16FF+ FinFET 3D transistors.

Xilinx estimates the UltraScale+ family will deliver 2–5X greater system level performance/watt over 28nm devices. Key applications are expected to include LTE Advanced and early 5G wireless, terabit wired communications, automotive ADAS, and industrial Internet-of-Things (IoT).

Some highlights:

  • Memory Enhanced Programmable Devices: UltraRAM attacks one of the largest bottlenecks affecting FPGA- and SoC-based system performance and power by enabling SRAM integration. The new on-chip memory could be used for deep packet and video buffering. UltraRAM scales up to 432 Mbits in a variety of configurations.
  • SmartConnect Technology: Interconnect optimization technology for FPGAs. It provides additional 20-30 percent performance, area, and power advantages through intelligent system-wide interconnect optimization. While the UltraScale architecture attacks the silicon-level interconnect bottleneck through re-architected routing, clocking, and logic fabric, SmartConnect applies interconnect topology optimizations to match design-specific throughput and latency requirements while reducing interconnect logic area. 
  • 3D-on-3D Technology: The high end of the UltraScale+ portfolio leverages the combined power of 3D transistors and third generation of Xilinx 3D ICs. Just as FinFETs enable a non-linear improvement in performance/watt over planar transistors, 3D ICs enable a non-linear improvement in systems integration and bandwidth/watt over monolithic devices.   
  • Heterogeneous Multi-processing Technology: The new Zynq UltraScale+ MPSoCs include all of the aforementioned FPGA technologies with an unprecedented level of heterogeneous multi-processing, deploying the "the right engines for the right tasks." These new devices deliver approximately 5X system level performance/watt relative to previous alternatives.  At the center of the processing-subsystem is the 64-bit quad-core ARM® Cortex®-A53 processor, capable of hardware virtualization, asymmetric processing, and full ARM TrustZone® technology support.

"Xilinx is delivering a generation ahead of value with 16nm FinFET FPGAs and MPSoCs to a variety of next generation applications," said Victor Peng, executive vice president and general manager of the Programmable Products Group at Xilinx.  "Our new UltraScale+ 16nm portfolio delivers 2-5X higher system performance-per-watt, a dramatic leap in system integration and intelligence, and the highest level of security and safety required by our customers. These capabilities enable Xilinx to significantly expand its available market."

Early customer engagements are in process for the UltraScale+ families. First tape out and early access release of the design tools are scheduled for the second calendar quarter of 2015.

http://www.xilinx.com/products/technology/ultrascale.html

Thursday, October 8, 2015

Qualcomm Samples 24-core Server Chip based on ARMv8-A

Qualcomm has begun sampling a 24-core SoC based on the ARMv8-A instruction set and built using advanced FinFet technology.  The company's Server Development Platform (SDP) is aimed at high-density data centers.

Qualcomm also announced two key partnerships.  The company is partnering with Xilinx to deliver heterogeneous computing solutions for data centers with Qualcomm’s server processor and Xilinx FPGAs. Qualcomm is partnering with Mellanox to enable advanced, cost effective platforms for servers and storage that deliver the fastest, most efficient interconnect solutions for data transfer and analysis with Qualcomm’s server CPU and Mellanox’s Ethernet and InfiniBand interconnect solutions.

"The release of our evaluation system is a major milestone for Qualcomm Technologies. As data centers evolve to support the exponential growth and innovation in data, connectivity and cloud services, Qualcomm Technologies is creating an ecosystem to meet the needs of these next-generation data centers with Qualcomm-based server technologies. Our customers are eager to test and evaluate our Server Development Platform and begin porting their software. We are incorporating their feedback into our product offering with the goal of ensuring system and software readiness by the time we are in full production,” stated Anand Chandrasekher, senior vice president, Qualcomm Technologies.

http://www.qualcomm.com

Tuesday, July 7, 2015

Xilinx Collaborates with China Mobile on 5G Fronthaul Interface

Xilinx is working with China Mobile Research Institute (CMRI) for the development of the next generation fronthaul interface (NGFI) for 5G. Fronthaul is the link between the baseband and radio units, which are expected to be distributed in 5G architectures.

Specifically, Xilinx is contributing to the NGFI eco-system with a validated NGFI reference design on its Zynq SoC platform. The reference design, which can easily be migrated to other Zynq and Zynq UltraScale+ MPSoC devices, will serve as a baseline framework for 4.5G/5G wireless network research.

"It's time to rethink current fronthaul solutions and addressing the major challenges for CRAN deployment is critical," said Dr. Chih-Lin I, chief scientist of China Mobile Research Institute. "New efficient and flexible fronthaul solutions are being worked on for the enablement of large scale CRAN deployment and our work with Xilinx will surely accelerate the delivery of such solutions."

"Current 'hard' mobile networks are plagued with a number of serious challenges including time to market, service innovation, energy efficiency, TCO and interoperability," said Sunil Kar, vice president of wireless communications at Xilinx. "Through our close collaboration with China Mobile Research Institute, we are working to address these challenges and identify the key technologies and components for highly optimized next generation fronthaul interfaces."

http://labs.chinamobile.com/cran/wp-content/uploads/White%20Paper%20of%20Next%20Generation%20Fronthaul%20Interface.PDF
http//www.xilinx.com

Sunday, March 22, 2015

Xilinx Releases 100G 802.3bj Reed-Solomon FEC

Xilinx has begun shipping its 100G IEEE 802.3bj Reed-Solomon FEC (RS-FEC) IP for data center, service provider, and enterprise applications.

The 100G RS-FEC LogiCORE IP solution seamlessly connects to Xilinx's integrated or soft 100G Ethernet MAC IP running on Virtex® UltraScale, enabling emerging optical solutions such as SR4, CWDM4, PSM4 or ER4f.

Xilinx is the first to demonstrate a complete 100G RS-FEC IP solution with Finisar and TE Connectivity (TE) optics showcased in multiple demonstrations at OFC 2015,

http://www.xilinx.com/esp/wired/wired_ip_resources.htm#connectivity

Monday, March 2, 2015

Xilinx and BEEcube Launch 5G Massive MIMO Prototyping Platform

Xilinx and BEEcube announced a highly scalable prototyping platform for 5G massive MIMO antenna systems.

The new MegaBEE prototyping platform supports up to 256x256 antennas and provides all the elements necessary to put a massive MIMO system on the air within LTE bands and without external hardware.  The platform uses Xilinx’s Zynq All Programmable SoC.

MegaBEE said its clocking structure paves the way for antenna modules to be dispersed over a three mile radius while maintaining phase coherence, enabling the system to be used for distributed MIMO as well as massive MIMO systems with greater coverage and capacity.

"Xilinx devices have long been used in wireless infrastructure equipment due to their unique properties of being fully programmable and high performance. MegaBEE's Linux cluster for distributed control is one of the most innovative uses of Zynq's dual ARM cores that I have seen," said Ivo Bolsens, Xilinx CTO and senior vice president.

"The MegaBEE platform delivers all the required elements for 5G massive MIMO prototyping in one box, greatly simplifying the task of building a system and freeing designers up to focus on algorithms instead of the interfaces around the periphery of their design," said Chen Chang, BEEcube founder and CEO. "Our tier one customers have pushed us hard to create an easy-to-use yet powerful MIMO prototyping platform and together with Xilinx, we've done just that."

http://www.beecube.com/products/MegaBEE.asp
http://www.xilinx.com/products/silicon-devices/soc.html

http://www.beecube.com

Monday, February 23, 2015

Xilinx Outlines its 16nm UltraScale+ Family of FPGAs

Xilinx introduced its next-generation 16nm UltraScale+ family of FPGAs, featuring new memory, 3D-on-3D and multi-processing SoC (MPSoC) technologies.

The UltraScale+ family also includes a new interconnect optimization technology and will leverage TSMC's 16FF+ FinFET 3D transistors.

Xilinx estimates the UltraScale+ family will deliver 2–5X greater system level performance/watt over 28nm devices. Key applications are expected to include LTE Advanced and early 5G wireless, terabit wired communications, automotive ADAS, and industrial Internet-of-Things (IoT).

Some highlights:

  • Memory Enhanced Programmable Devices: UltraRAM attacks one of the largest bottlenecks affecting FPGA- and SoC-based system performance and power by enabling SRAM integration. The new on-chip memory could be used for deep packet and video buffering. UltraRAM scales up to 432 Mbits in a variety of configurations.
  • SmartConnect Technology: Interconnect optimization technology for FPGAs. It provides additional 20-30 percent performance, area, and power advantages through intelligent system-wide interconnect optimization. While the UltraScale architecture attacks the silicon-level interconnect bottleneck through re-architected routing, clocking, and logic fabric, SmartConnect applies interconnect topology optimizations to match design-specific throughput and latency requirements while reducing interconnect logic area. 
  • 3D-on-3D Technology: The high end of the UltraScale+ portfolio leverages the combined power of 3D transistors and third generation of Xilinx 3D ICs. Just as FinFETs enable a non-linear improvement in performance/watt over planar transistors, 3D ICs enable a non-linear improvement in systems integration and bandwidth/watt over monolithic devices.   
  • Heterogeneous Multi-processing Technology: The new Zynq UltraScale+ MPSoCs include all of the aforementioned FPGA technologies with an unprecedented level of heterogeneous multi-processing, deploying the "the right engines for the right tasks." These new devices deliver approximately 5X system level performance/watt relative to previous alternatives.  At the center of the processing-subsystem is the 64-bit quad-core ARM® Cortex®-A53 processor, capable of hardware virtualization, asymmetric processing, and full ARM TrustZone® technology support.

"Xilinx is delivering a generation ahead of value with 16nm FinFET FPGAs and MPSoCs to a variety of next generation applications," said Victor Peng, executive vice president and general manager of the Programmable Products Group at Xilinx.  "Our new UltraScale+ 16nm portfolio delivers 2-5X higher system performance-per-watt, a dramatic leap in system integration and intelligence, and the highest level of security and safety required by our customers. These capabilities enable Xilinx to significantly expand its available market."

Early customer engagements are in process for the UltraScale+ families. First tape out and early access release of the design tools are scheduled for the second calendar quarter of 2015.

http://www.xilinx.com/products/technology/ultrascale.html

Tuesday, February 17, 2015

Xilinx and BEEcube Deliver 5G Prototyping Platform

Xilinx and BEEcube have teamed up to deliver the world's first millimeter wave (mmWave) prototyping platform solution for 5G.

The solution consists of Xilinx's newest 256QAM 500MHz mmWave modem IP coupled with the BEEcube BEE7 baseband platform.  This provides a complete "out of the box" solution addressing the 60GHz backhaul market. The integrated BEEcube BEE7 baseband platform connects to two 60GHz wideband transceivers and phased-array antennas enhancing the performance by virtue of increased absolute frequency range and channel bandwidth. In addition, the highly configurable point-to-point 500MHz mmWave modem IP from Xilinx includes, among other features, adaptive modulation and bandwidth, high-performance LDPC FEC, adaptive DPD, I/Q imbalance correction, automatic frequency recovery, a hybrid decision-directed equalizer, and supports speeds up to 3.5Gbps in single polarization mode.

"5G will increase cellular network capacity by a factor of 1,000 and the use of mmWave frequencies is critical to address the growing need," said Dr. Bob Brodersen, Co-Founder Berkeley Wireless Research Center and Chairman of the Board at BEEcube. "Existing tools for prototyping at mmWave frequencies are very limited and do not offer good integration. With no competing offerings in this frequency range, the introduction of this mmWave prototyping solution fills a huge gap as companies race to prototype 5G systems."

http://www.xilinx.com/products/intellectual-property/millimeter-wave-modem.html

Monday, November 24, 2014

Xilinx and NXP Collaborate on LTE-A and 5G

Xilinx and NXP have been working together to combine Xilinx's newest crest factor reduction (CFR) and digital pre-distortion (DPD) SmartCORE IP with NXP's Gen9 LDMOS RF highly efficient power amplifier technology. The combination of NXP's advanced power amplifier devices and Xilinx All Programmable devices and radio IP enables customers to implement smaller, lighter and higher reliability radios suitable for use in next-generation wireless infrastructure equipment.

Power amplifiers of higher efficiency achieve the same radio output power and enable a CapEx saving through the use of lower power rated devices and reduced cooling mechanics. Xilinx's Zynq®-7000 All Programmable SoC is the first hardware and software programmable device supporting the latest generation of CPRI at 10.1Gbps and JESD204B at 12.5 Gbps line rates.

Xilinx's latest CFR and DPD IP now support up to 100MHz of radio bandwidth in single RAT configurations in addition to supporting MC-GSM with frequency hopping in single RAT or multi-RAT configurations up to 75MHz.

"Xilinx and NXP will continue to collaborate on future technology standards such as LTE-A and 5G, and expand the system impact with the most efficient and easy to adopt combination of radio algorithms and power amplifier technology," saidDavid Hawke, director of wireless communications at Xilinx.

http://www.xilinx.com
http://www.nxp.com


Sunday, November 16, 2014

Xilinx Announces 25G Ethernet IP for FPGAs

Xilinx announced low latency 25G Ethernet IP for FPGAs aimed at data center switching.

The low latency 25G Ethernet MAC and PCS LogiCORE IP solution supports the new 25G Ethernet Consortium specification and will be aligned with the industry's continuing advancements in next-generation processors, which are doubling their performance for tomorrow's data center servers.

Xilinx is demonstrating the 25G Ethernet MAC and PCS LogiCORE IP solution at this week's Supercomputing in New Orleans. The live demonstration utilizes two Virtex UltraScale VCU107 boards communicating over four channels of 25G Ethernet through 5 meters of direct attached copper cable and two QSFP+ modules.

http://www.xilinx.com/esp/datacenter/data_center_ip.htm
http://www.xilinx.com

Thursday, October 16, 2014

Xilinx Posts Flat Quarterly Sales but Profitability Exceeds Guidance

Xilinx posted second quarter fiscal 2015 sales of $604 million, down 1% from the prior quarter and up 1% from the same quarter of the prior fiscal year.  Second quarter fiscal 2015 net income was $172 million or $0.62 per diluted share.

"September quarter sales were in line with our guidance, but our profitability surpassed our expectations.  Operating margin was 33% in the September quarter, up from 27% in the same quarter a year ago," said Moshe Gavrielov, Xilinx President and Chief Executive Officer.  "For the December quarter, we are forecasting a strong recovery in 28nm sales driven by a broad base of applications.  We continue to target approximately $600 million in 28nm sales for fiscal year 2015, up nearly 60% from the prior fiscal year."

http://www.xilinx.com

Monday, November 11, 2013

Xilinx Ships 20nm FPGA

Xilinx announced the first customer shipment of the semiconductor industry's first 20nm product manufactured by TSMC, and the PLD industry's first 20nm All Programmable device.

Xilinx UltraScale devices offer an ASIC-class programmable architecture coupled with the "Vivado" ASIC-strength design suite and recently introduced "UltraFast" design methodology.

"This announcement underscores our first-to-market leadership commitment of delivering high-performance FPGAs," said Victor Peng, senior vice president and general manager of products at Xilinx. "The next generation starts now with the  shipment of our new UltraScale devices, building upon the tremendous momentum we have established with our 7 series."

Target applications include systems for 400G OTN, packet processing and traffic management, 4X4 Mixed Mode LTE, WCDMA Radio, 4K2K and 8K displays, Intelligence Surveillance and Reconnaissance (ISR), and high-performance computing applications for the data center.

Initial UltraScale device samples are shipping now.  General sampling begins in Q12014.

http://www.xilinx.com

Tuesday, October 8, 2013

Xilinx Releases Virtex-7 FPGA Kit for 40GbE Designs

Xilinx released its Virtex-7 FPGA VC709 Connectivity Kit for high-bandwidth and high-performance applications, such as network interface cards for security, network monitoring, and high frequency trading appliances.

The Virtex-7 FPGA kit is aimed at developers needing to prototype their low power, high performance, single-chip PCIe Gen3, 40Gbps Ethernet applications.  The kit provides a fully validated and supported targeted reference design that integrates the entire PCIe Gen3, AXI, Ethernet and DDR3 subsystem with both the HDL and the entire software stack.  An evaluation license of the Northwest Logic DMA IP core is also included in the connectivity kit.

http://www.xilinx.com/vc709

See also