Showing posts with label FPGA. Show all posts
Showing posts with label FPGA. Show all posts

Tuesday, September 12, 2017

Huawei picks Xilinx FPGAs for Accelerated Cloud Server

Huawei has selected Xilinx Virtex UltraScale+ FPGAs to power their first FP1 instance as part of a new accelerated cloud service. The Huawei FPGA Accelerated Cloud Server (FACS) is a platform that enables users to develop, deploy and publish new FPGA-based services and applications on Huawei Public Cloud.

Xilinx said its FPGAs can provide a 10-50x speed-up for compute intensive cloud applications such as machine learning, data analytics, and video processing.  Xilinx FPGAs can be reconfigured in less than a second to a different design that is hardware optimized for its next workload.

"The Huawei FACS is a fully integrated hardware and software platform offering developer-to-deployment support with best-in-class industry tool chains and access to Huawei's significant FPGA engineering expertise," said Steve Langridge, Director, Central Hardware Institute, Huawei Canada Research Center.

The FPGA Accelerated Cloud Server now available on the Huawei Public Cloud.

http://www.hwclouds.com/product/fcs.html
http://www.huaweicloud.com

Monday, July 10, 2017

Baidu deploys Xilinx FPGAs for cloud acceleration

Xilinx announced that Baidu has deployed Xilinx FPGA-based application acceleration services into its public cloud, specifically for the Baidu FPGA Cloud Server, a new service that leverages Xilinx Kintex FPGAs, tools and the software required for hardware-accelerated data centre applications such as machine learning and data security.

The Baidu FPGA Cloud Server provides a complete FPGA-based hardware and software development environment, including hardware and software design examples, and is designed to help users quickly develop and migrate applications with reduced development costs.

The Baidu service is based on each FPGA instance serving as a dedicated acceleration platform that is not shared between instances or users. The design examples provided services including cover deep learning acceleration, encryption and decryption.

Xilinx claims that FPGA-enabled servers can deliver a 10x to 80x performance per watt advantage compared to CPU-only servers. In addition, as they are dynamically reconfigurable, Xilinx FPGAs can support a range of workloads, including machine learning, data analytics, security and video processing.



  • Separately, Baidu announced a partnership with Microsoft for its new open source autonomous driving platform, Apollo. Baidu unveiled Apollo in April, featuring cloud services, software and reference hardware/vehicle platforms, and expects the technology will be running on roads by late 2020.
  • In addition, Conexant, a provider of audio and voice technology solutions, announced it was collaborating with Baidu to release development kits and reference designs for device makers to develop far-field voice-enabled artificial intelligent (AI) devices running on Baidu's DuerOS platform. The development kits and reference designs will feature Conexant's CX20924 4-microphone and CX20921 2-microphone voice input processing solutions and DuerOS, a conversation-based AI system that enables access to a voice-activated digital assistant for mobile phones, TVs and other devices.

Tuesday, May 9, 2017

Flex Logix, developer of embedded FPGA technology, raises $5m

Flex Logix Technologies, headquartered in Mountain View, California, a supplier of embedded FPGA IP and software:

a.         Founded in March 2014 to develop solutions for reconfigurable RTL in chip and system designs employing embedded FPGA IP cores and software.

b.         Offering the EFLX technology platform designed to significantly reduce design and manufacturing risks, accelerate technology development and provide greater flexibility for customers' hardware.

c.         Which in October 2015 announced it had raised $7.4 million in a financing round was led by dedicated hardware fund Eclipse Ventures (formerly the Formation 8 hardware fund), with participation from founding investors Lux Capital and the Tate Family Trust.

Announced it has secured $5 million in Series B equity financing in a round led by existing investors Lux Capital and Eclipse Ventures, with participation from the Tate Family Trust.

Flex Logix stated that new funding will be used to expand its sales, applications and engineering teams to meet the growing customer demand for its embedded FPGA platform in applications including networking, government, data centres and deep learning.

Targeting chips in multiple markets, the Flex Logix EFLX platform can be used with networking chips with reconfigurable protocols, data centre chips with reconfigurable accelerators, deep learning chips with real-time upgradeable algorithms, base stations chips with customisable features and MCU/IoT chips with flexible I/O and accelerators. The company noted that EFLX is currently available for popular process nodes and is being ported to further process nodes based on customer demand.

The Flex Logix technology offers high-density blocks of programmable RTL in any size together with the key features customers require. The solution allows designers to customise a single chip to address multiple markets and/or upgrade the chip while in the system to meet to changing standards such as networking protocols. It also allows customers to update chips with new deep learning algorithms and implement their own versions of protocols in data centres.

Regarding the new funding, Peter Hebert, managing partner at Lux Capital, said, "I believe that Flex Logix's embedded FPGA has the potential to be as pervasive as ARM's embedded processors… the company's software and silicon are proven and in use at multiple customers, paving the way to become one of the most widely-used chip building blocks across many markets and for a range of applications".

While Pierre Lamond, partner at Eclipse Ventures, commented, "The Flex Logix platform is the… most scalable and flexible embedded FPGA solution on the market, delivering competitive advantages in time to market, engineering efficiency, minimum metal layers and high density… the patented technology combined with an experienced management team led by Geoff Tate, founding CEO of Rambus, position the company for rapid growth".


Monday, April 10, 2017

Microsemi integrates Athena Cryptographic Processor into FPGAs

Microsemi and The Athena Group, a supplier of security, cryptography, anti-tamper and signal processing IP cores, announced that Athena's TeraFire cryptographic microprocessor has been integrated into Microsemi's recently introduced PolarFire FPGA 'S class' family.

Athena's TeraFire cryptographic microprocessor technology is designed to address cybersecurity requirements for a range of industries via support for the most commonly used cryptographic algorithms, including those certified for military/government use by the U.S. NIST's Suite B, as well as those recommended in the U.S. Commercial National Security Algorithm (CNSA) suite. TeraFire also supports algorithms and key sizes commonly used in Internet communications protocols, such as TLS, IPSec, MACSec and KeySec.

Microsemi's secure, cost-optimised PolarFire FPGAs offer low power consumption at mid-range densities with 12.7 Gbit/s SerDes transceivers, as well as high reliability, and target applications including wireline access networks and cellular infrastructure, smart connected factory, functional safety and secure communications.

PolarFire FPGAs' transceivers also offer support for multiple serial protocols, making them suitable for communications applications with 10 Gigabit Ethernet, CPRI, JESD204B, Interlaken and PCIe. In addition, the ability to implement serial gigabit Ethernet (SGMII) on general purpose input/output (GPIO) enables multiple 1 Gigabit Ethernet links to be supported.

Microsemi noted that the TeraFire cryptographic microprocessor enables a significant improvement in built-in cryptographic capabilities compared to SRAM-based FPGAs and has been adopted by both defence and commercial customers as a result of its flexibility and efficiency.

Athena's TeraFire cryptographic microprocessors can operation at up to 200 MHz. The TeraFire core provides advanced countermeasures against side-channel analysis (SCA) techniques such as DPA and differential electro-magnetic analysis (DEMA) that could otherwise be used to extract secret keys from the device, with supported algorithms that use a secret or private key offered with countermeasures against SCA.

Microsemi's PolarFire 'S class' FPGAs equipped with Athena TeraFire cryptographic microprocessor are scheduled to be available by the end of the second quarter of 2017.

https://www.microsemi.com/

Friday, March 17, 2017

Xilinx to Demo FPGAs in 400G Ethernet, FlexE

At this week's Optical Fiber Communications (OFC) Conference and Exhibition in Los Angeles Xilinx will debut a number of solutions for high speed data center interconnect (DCI) solutions.

Xilinx will participate in a 400GE multi-vendor network demo featuring the world's first standards-based 400GE MAC and PCS IP in a Xilinx Virtex UltraScale+™ VU9P FPGA. Showcasing the emerging 400GE standard interoperability between multiple vendors, the demo illustrates the Xilinx 400G solution connecting to a Finisar 400GE CFP8 module which in turn connects to a Spirent 400G test module in the Ethernet Alliance booth.

Xilinx will also showcase a complete FlexE 1.0 solution with bonding, sub-rating and channelization on its UltraScale+ FPGAs. This solution demonstrates how multiple clients can be transported using FlexE and highlights the ability of FlexE to carry larger data pipes and match them to transport links for optimal utilization of the link budget. This solution allows network operators to maximize optical performance and lower operating costs over existing infrastructure.

A third demo shows how LLDP packets can be snooped on transport line cards to allow a SDN controller to build a network topology for automation integral to data center networks. It also shows the use of IEEE compliant MACsec to encrypt and authenticate the link for security. As more and more critical applications and data migrate to the cloud, MACsec provides data encryption and authentication to preserve privacy. Such a solution is mandatory in front of a traditional DSP to provide a complete DCI solution.

Another demonstration showcases Xilinx's new 56G PAM-4 transceiver test chip in 16nm FinFET delivering optimized performance for backplane and LR applications.

http://www.xilinx.com

Thursday, March 9, 2017

Alibaba Looks to Intel FPGAs for Cloud Acceleration Service

Alibaba Cloud (Aliyun), is kicking off a pilot program with Intel for a cloud-based FPGA (field programmable gate array) acceleration service.

Specifically, Aliyun will use Intel Arria 10 FPGAs, Intel Xeon processor-based servers and software development tools for application acceleration as a ready-to-go preconfigured infrastructure.  The Aliyun service offers systems designers cloud-based workload acceleration as an alternative to investing in on-premises FPGA infrastructure.

“At Alibaba Cloud, we offer customers access to a number of services in the cloud, and adding an FPGA-based acceleration offering means they can access that powerful computing without the cost or requirement of building out their own infrastructure,” said Jin Li, senior director, Alibaba Cloud. “This service greatly adds to our value as a leading provider of highly scalable cloud computing and data management services that provide businesses with flexible, reliable connectivity.”

“Intel FPGAs are enabling exciting new business models such as Alibaba’s approach of using FPGAs to accelerate diverse workloads via cloud services,” said Dan McNamara, corporate vice president and general manager, Intel Programmable Solutions Group. “In addition, Intel offers customers scalable solutions for accelerated computing with its data center leadership in Intel Xeon processors, FPGAs, optimized tools and software, and a global partner ecosystem across the spectrum of deployment models.”

http://www.intel.com

Friday, February 24, 2017

Xilinx Integrates RF analogue Tech into All Programmable MPSoCs

Xilinx has announced what it claims is a disruptive integration and architectural technique for 5G wireless with the addition of RF-class analogue technology into its 16 nm All Programmable MPSoC products.

Xilinx's new All Programmable RFSoCs eliminate the need for discrete data converters, providing a claimed 50-75% reduction in terms of power and footprint for 5G massive MIMO and millimetre-wave (mmWave) wireless backhaul applications.

The company noted that large scale 2D antenna arrays will be a key element for increasing spectral efficiency and network densification for 5G networks. The integration of ADCs and DACs into Xilinx's All Programmable SoC devices is designed to enable radio and wireless backhaul units to meet previously unattainable power and form factor demands, while also allowing higher channel density.

In addition, the new RFSoC devices can also help manufacturers streamline design and development cycles and meet 5G deployment timelines.

Xilinx's new All Programmable RFSoC devices offer features including:

1. Direct RF sampling to simplify analogue design and enhance accuracy and enable a smaller form factor and lower power consumption.

2. 12-bit ADCs supporting up to 4 GS/s, high channel count, with digital down-conversion.

3. 14-bit DACs supporting up to 6.4 GS/s, high channel count and digital up conversion.

The new RFSoC integrated subsystem specifically targets a range of applications including high bandwidth remote radio and backhaul systems for 5G deployments and remote node architectures (R-PHY) for DOCSIS 3.1 cable broadband systems.


Thursday, February 16, 2017

Microsemi Unveils low power FPGA with 12.7 Gbps SerDes

Microsemi, a provider of semiconductor solutions, has announced availability of its new cost-optimised PolarFire FPGA product family, which it claims offers the lowest power mid-range density solution with 12.7 Gbit/s SerDes transceivers for applications including wireline access networks and cellular infrastructure and for industry 4.0 markets, encompassing industrial automation and Internet of Things (IoT).

Microsemi's new PolarFire FPGAs are designed to support cost-effective bandwidth processing capabilities for converged 10 Gbit/s ports with low power usage. The new FPGA products are also designed to address increasing cyber security threats and reliability concerns that face deep submicron SRAM-based FPGAs as they relate to single event upsets (SEUs) in the configuration memory.

In the communications market, the new devices target applications including wireline access, network edge, metro (1 to 40 Gbit/s); wireless heterogeneous networks, wireless backhaul, smart optical modules and video broadcasting. The devices are also suitable for applications in the defence and aerospace market, secure wireless communications, radar and aircraft networking, actuation and control.

The devices' cost-optimised architecture uses 28 nm silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile process technology on standard CMOS, while it incorporates hardened I/O gearing logic for DDR memory and low-voltage differential signalling (LVDS), high performance security IP and is claimed to be the only low cost device with clock and data recovery (CDR) capable 1.6 Gbit/s I/Os.

In addition, in collaboration with Silicon Creations Microsemi has developed a compact 12.7 Gbit/s transceiver offering total power consumption of less than 90 mWs at 10 Gbit/s. Featuring low device static power of 25 mW at 100K logic elements, zero inrush current and Flash*Freeze mode enabling standby power of 130 mWs at 25 degrees C, PolarFire devices are claimed to be up to 50% lower power than competing FPGAs for similar applications.

The FPGA family also provides high reliability via inherent immunity to configuration SEUs, along with built- in single error correction and double error detectin (SECDED), plus memory interleaving on large static random access memory (LSRAMs) and system controller suspend mode for safety critical designs.

PolarFire FPGAs additionally offer Cryptography Research Incorporated (CRI) patented differential power analysis (DPA) bitstream protection, integrated physically unclonable function (PUF), 56 Kbytes of secure embedded non-volatile memory (eNVM), tamper detectors and countermeasures, true random number generators, integrated Athena TeraFire EXP5200B Crypto Co-processors (Suite B capable) and a CRI DPA countermeasures pass-through license.

Microsemi's new PolarFire FPGA product family is currently shipping to early access customers and is scheduled to sample for general availability in the second quarter of 2017. Microsemi noted that with the device it is actively engaged with select customers through its early access program, while adoption of the products has already started.

Regarding the new products, Shakeel Peera, senior director, SoC product marketing at Microsemi, noted,

"Combining the availability of the cost-effective PolarFire FPGAs with Microsemi's portfolio of application-
specific standard products (ASSPs) enables end-to-end solutions in timing, voice processing, storage, OTN switching and transport, and power management across multiple market segments".

Monday, February 13, 2017

Intel Previews Cyclone FPGAs

Intel introduced its Cyclone 10 family of field programmable gate arrays (FPGAs) aimed at automotive, industrial automation, pro audio visual and vision systems applications.

The company said the new Cyclone 10 GX is unique among other low-cost FPGAs as it can support 10G transceivers and hard floating point DSP (digital signal processing). It offers 2-times the performance increase over the previous generation of Cyclone. The architectural innovation in the implementation of IEEE 754 single-precision hardened floating-point DSP blocks can enable processing rates up to 134 GFLOPs (giga floating-point operations per second). This is important for engineers needing higher performance using the FPGA for applications such as motion or motor control systems.

The Cyclone 10 FPGA family will be available in the second half of 2017, along with evaluation kits and boards, and the latest version of Quartus, the Intel FPGA programming software.

http://www.intel.com


  • Intel completed its acquisition of Altera in January 2016. 

Monday, February 6, 2017

Aquantia and AptoVision Target Software-Defined Video over Ethernet

Aquantia, which specializes in high-speed Ethernet connectivity solutions for data centers, enterprise infrastructure and client connectivity,is working with AptoVision, the pioneer in video over Ethernet technology, on the industry's first fully integrated single-chip solution for implementing Software-Defined Video over Ethernet on 10GBASE-T infrastructure.

The collaboration combines Aquantia's AQcite FPGA-programmable Multi-Gigabit Ethernet PHY with AptoVision's BlueRiver technology to support the new SDVoE standard.

Aquantia recently announced the AQcite product line, and specifically the AQLX107, the industry's first FPGA-programmable multi-gigabit Ethernet PHY device targeting a vast range of applications such as Audio-Visual (AV) over Ethernet, machine vision, data center, enterprise, 5G wireless, industrial, metro environments and more. AQLX107 integrates a programmable FPGA processing fabric with a 10GBASE-T PHY, to create a single-chip hardware platform.  Combined with AptoVision's BlueRiver technology, the AQLX107 can be used to transmit true 4K60 video across off-the-shelf 10G Ethernet networks and standard category cable with zero frame latency.  Audio and video processing, including upscaling, downscaling, and multi-image compositing are all realizable on the SDVoE hardware and software platform made possible by the AQLX107.

"By deploying the combination of Aquantia's AQcite FPGA-Programmable multi-gigabit Ethernet PHY with AptoVision's BlueRiver NT+ offering, our customers enjoy the benefit of a power and cost optimized solution while leveraging the large ecosystem of Ethernet networking equipment to scale their pro-AV architecture," said Amir Bar-Niv, VP Marketing at Aquantia. "We're excited to drive SDVoE into the market together with AptoVision and the other partners of the alliance with our unique single-chip solution."

http://www.aquantia.com


Thursday, November 3, 2016

Private Equity Firm Acquires Lattice Semi for $1.3 Billion - FPGAs

Canyon Bridge Capital Partners agreed to acquire all outstanding shares of Lattice Semiconductor Corporation (NASDAQ:LSCC) for approximately $1.3 billion inclusive of Lattice’s net debt, or $8.30 per share in cash. This represents a 30% premium to Lattice’s last trade price on November 2, 2016, the last trading day prior to announcement.

Lattice supplies low power FPGA, video ASSP, 60 GHz millimeter wave, and IP products to the consumer, communications, industrial, computing, and automotive markets worldwide. The company is based in Portland, Oregon.

Darin G. Billerbeck, President and Chief Executive Officer of Lattice, commented, “We are pleased to announce the transaction today with Canyon Bridge, which will unlock tremendous value for shareholders. This transaction is the culmination of an extensive review process with our Board, financial and legal advisers, and it delivers certain and immediate cash value to shareholders while reducing our execution risk. We are excited to leverage Canyon Bridge’s resources and market connections as we enhance our focus on executing our long-term strategic plan of continued innovation. Importantly, we will operate as a standalone subsidiary after the acquisition and do not expect any changes in our operations or our unwavering commitment to continued innovation for our customers.”

Ray Bingham, Founding Partner, Canyon Bridge, noted, “Lattice’s low-power FPGA franchise, along with its video connectivity and wireless solutions, make it a compelling, strategic investment. We expect the Company will continue to leverage its existing customer relationships with major OEMs globally, while further broadening the role of its technology solutions and accelerating its strategic plans.”

http://ir.latticesemi.com/

Sunday, January 31, 2016

Xilinx Ships 16nm Virtex UltraScale+ FinFET FPGAs

Xilinx announced first customer shipment of its Virtex UltraScale+ FPGA, the industry's first high-end FinFET FPGA built using TSMC's 16FF+ process.

The Virtex UltraScale+ devices join the Zynq UltraScale+ MPSoCs and Kintex UltraScale+ FPGAs showcasing the availability of all three families of the Xilinx 16nm portfolio. The UltraScale+ portfolio provides 2 – 5x greater system-level performance/watt over 28nm devices and is suited for LTE Advanced and early 5G Wireless, Automotive ADAS, Cloud Computing, Industrial Internet-of-Things (IoT), SDN/NFV, and Video/Vision markets.      

Xilinx said it is actively engaged with more than one hundred customers on the UltraScale+ portfolio with design tools, and has already shipped devices and/or boards to over sixty of these customers.

"The successful delivery of our Virtex UltraScale+ FPGA marks the availability of all three UltraScale+ 16nm families, which are already providing more than one hundred customers with the ability to develop next generation designs using cutting edge FinFET-based devices, development boards and tools. Our "Three-Peat" execution – with three consecutive generations of leadership technology at 28nm, 20nm, and now at 16nm – showcases our sustained commitment to being first to market with the most advanced products in our industry," said Victor Peng, executive vice president and general manager of the Programmable Products Group at Xilinx.

http://www.xilinx.com

Xilinx Outlines its 16nm UltraScale+ Family of FPGAs

Xilinx introduced its next-generation 16nm UltraScale+ family of FPGAs, featuring new memory, 3D-on-3D and multi-processing SoC (MPSoC) technologies.

The UltraScale+ family also includes a new interconnect optimization technology and will leverage TSMC's 16FF+ FinFET 3D transistors.

Xilinx estimates the UltraScale+ family will deliver 2–5X greater system level performance/watt over 28nm devices. Key applications are expected to include LTE Advanced and early 5G wireless, terabit wired communications, automotive ADAS, and industrial Internet-of-Things (IoT).

Some highlights:

  • Memory Enhanced Programmable Devices: UltraRAM attacks one of the largest bottlenecks affecting FPGA- and SoC-based system performance and power by enabling SRAM integration. The new on-chip memory could be used for deep packet and video buffering. UltraRAM scales up to 432 Mbits in a variety of configurations.
  • SmartConnect Technology: Interconnect optimization technology for FPGAs. It provides additional 20-30 percent performance, area, and power advantages through intelligent system-wide interconnect optimization. While the UltraScale architecture attacks the silicon-level interconnect bottleneck through re-architected routing, clocking, and logic fabric, SmartConnect applies interconnect topology optimizations to match design-specific throughput and latency requirements while reducing interconnect logic area. 
  • 3D-on-3D Technology: The high end of the UltraScale+ portfolio leverages the combined power of 3D transistors and third generation of Xilinx 3D ICs. Just as FinFETs enable a non-linear improvement in performance/watt over planar transistors, 3D ICs enable a non-linear improvement in systems integration and bandwidth/watt over monolithic devices.   
  • Heterogeneous Multi-processing Technology: The new Zynq UltraScale+ MPSoCs include all of the aforementioned FPGA technologies with an unprecedented level of heterogeneous multi-processing, deploying the "the right engines for the right tasks." These new devices deliver approximately 5X system level performance/watt relative to previous alternatives.  At the center of the processing-subsystem is the 64-bit quad-core ARM® Cortex®-A53 processor, capable of hardware virtualization, asymmetric processing, and full ARM TrustZone® technology support.

"Xilinx is delivering a generation ahead of value with 16nm FinFET FPGAs and MPSoCs to a variety of next generation applications," said Victor Peng, executive vice president and general manager of the Programmable Products Group at Xilinx.  "Our new UltraScale+ 16nm portfolio delivers 2-5X higher system performance-per-watt, a dramatic leap in system integration and intelligence, and the highest level of security and safety required by our customers. These capabilities enable Xilinx to significantly expand its available market."

Early customer engagements are in process for the UltraScale+ families. First tape out and early access release of the design tools are scheduled for the second calendar quarter of 2015.

http://www.xilinx.com/products/technology/ultrascale.html

Saturday, October 10, 2015

Altera Demos FPGAs for CCAP Architecture

Altera demonstrated its new, flexible and upgradeable silicon solution for  multi-service operators (MSOs) adopting distributed CCAP (converged cable access platform) architecture.

The Altera DOCSIS Remote (MAC) PHY design, which is being demonstrated with partners Analog Devices, and Capacicom, enables cable operators to more efficiently and cost-effectively meet the ever-increasing need to segment cable networks, driven by the demand of high-speed Internet, unicast 4K video and other multimedia content.

The solution uses Altera Arria 10 FPGAs and Analog Devices' class-leading digital-to-analog converters (DACs) and analog-to-digital converters (ADCs), combined with Capacicom's MAC and PHY implementation, resulting in state-of-the-art radio frequency (RF) performance.

"With today's Altera FPGA portfolio and onward technology roadmap coupled with Capacicom's substantial experience in DOCSIS PHY and MAC layers, ADI has now found the perfect combination of partners to extend its leadership in high-performance analog into cable infrastructure solutions," said Carlton Lane, Analog Devices cable solutions manager. "ADI, Altera and Capacicom have set up a long-term collaboration to create the semiconductor industry reference platform for R - (MAC) PHY, with a continuing roadmap commitment to the lowest power consumption and cost per port."

Arria 10 FPGAs and SoCs deliver the highest performance at 20 nm.  The company said its Arria 10 FPGAs and SoCs are up to 40 percent lower power than previous generation FPGAs and SoCs and feature the industry's only hard floating-point digital signal processing (DSP) blocks with speeds up to 1,500 giga floating-point operations per second (GFLOPS).

http://www.altera.com/arria10

Monday, June 1, 2015

Intel to Acquire Altera for its Programmable Logic Devices

Intel agreed to acquire Altera a for $54 per share in an all-cash transaction valued at approximately $16.7 billion.

Altera, which is based in San Jose, California, offers programmable logic, process technologies, IP cores and development tools . Its portfolio includes its Stratix series FPGAs with embedded memory, digital signal processing (DSP) blocks, high-speed transceivers, and high-speed I/O pins. Altera's Arria system-on-chip solutions integrate an ARM-based hard processor and memory interfaces with the FPGA fabric using a high-bandwidth interconnect. These devices include additional hard logic such as PCI Express Gen2, multiport memory controllers, error correction code (ECC), memory protection and high-speed serial transceivers.

Altera had 2014 revenue of $1.9 billion, of which 44% of sales were for telecom/wireless, 22% for industrial/military/automotive, and 16% for networking/computer/storage. Altera holds about 39% market share of the PLD segment compared to 49% for Xilinx. The company was founded in 1983 and has approximately 3,000 employees.

"Intel's growth strategy is to expand our core assets into profitable, complementary market segments," said Brian Krzanich, CEO of Intel. "With this acquisition, we will harness the power of Moore's Law to make the next generation of solutions not just better, but able to do more. Whether to enable new growth in the network, large cloud data centers or IoT segments, our customers expect better performance at lower costs. This is the promise of Moore's Law and it's the innovation enabled by Intel and Altera joining forces."

"Given our close partnership, we've seen firsthand the many benefits of our relationship with Intel—the world's largest semiconductor company and a proven technology leader, and look forward to the many opportunities we will have together," said John Daane, President, CEO and Chairman of Altera. "We believe that as part of Intel we will be able to develop innovative FPGAs and system-on-chips for our customers in all market segments."

http://www.intel.com
http://www.altera.com

  • In February 2013, Altera announced that its next generation FPGAs will be based on Intel’s 14 nm tri-gate transistor technology. These next-generation products target ultra high-performance systems for military, wireline communications, cloud networking, and compute and storage applications. Under a partnership deal announced by the firms, Altera’s next-generation products will now include 14 nm, in addition to previously announced 20 nm technologies.

Monday, February 23, 2015

Xilinx Outlines its 16nm UltraScale+ Family of FPGAs

Xilinx introduced its next-generation 16nm UltraScale+ family of FPGAs, featuring new memory, 3D-on-3D and multi-processing SoC (MPSoC) technologies.

The UltraScale+ family also includes a new interconnect optimization technology and will leverage TSMC's 16FF+ FinFET 3D transistors.

Xilinx estimates the UltraScale+ family will deliver 2–5X greater system level performance/watt over 28nm devices. Key applications are expected to include LTE Advanced and early 5G wireless, terabit wired communications, automotive ADAS, and industrial Internet-of-Things (IoT).

Some highlights:

  • Memory Enhanced Programmable Devices: UltraRAM attacks one of the largest bottlenecks affecting FPGA- and SoC-based system performance and power by enabling SRAM integration. The new on-chip memory could be used for deep packet and video buffering. UltraRAM scales up to 432 Mbits in a variety of configurations.
  • SmartConnect Technology: Interconnect optimization technology for FPGAs. It provides additional 20-30 percent performance, area, and power advantages through intelligent system-wide interconnect optimization. While the UltraScale architecture attacks the silicon-level interconnect bottleneck through re-architected routing, clocking, and logic fabric, SmartConnect applies interconnect topology optimizations to match design-specific throughput and latency requirements while reducing interconnect logic area. 
  • 3D-on-3D Technology: The high end of the UltraScale+ portfolio leverages the combined power of 3D transistors and third generation of Xilinx 3D ICs. Just as FinFETs enable a non-linear improvement in performance/watt over planar transistors, 3D ICs enable a non-linear improvement in systems integration and bandwidth/watt over monolithic devices.   
  • Heterogeneous Multi-processing Technology: The new Zynq UltraScale+ MPSoCs include all of the aforementioned FPGA technologies with an unprecedented level of heterogeneous multi-processing, deploying the "the right engines for the right tasks." These new devices deliver approximately 5X system level performance/watt relative to previous alternatives.  At the center of the processing-subsystem is the 64-bit quad-core ARM® Cortex®-A53 processor, capable of hardware virtualization, asymmetric processing, and full ARM TrustZone® technology support.

"Xilinx is delivering a generation ahead of value with 16nm FinFET FPGAs and MPSoCs to a variety of next generation applications," said Victor Peng, executive vice president and general manager of the Programmable Products Group at Xilinx.  "Our new UltraScale+ 16nm portfolio delivers 2-5X higher system performance-per-watt, a dramatic leap in system integration and intelligence, and the highest level of security and safety required by our customers. These capabilities enable Xilinx to significantly expand its available market."

Early customer engagements are in process for the UltraScale+ families. First tape out and early access release of the design tools are scheduled for the second calendar quarter of 2015.

http://www.xilinx.com/products/technology/ultrascale.html

Wednesday, June 18, 2014

Intel to Integrate Xeon + FPGA On Chip to Accelerate Data Center Processing

Intel announced plans to integrate its Xeon processor with a coherent FPGA in a single package, socket compatible to a standard Xeon E5 processor. The goal to accelerate software defined infrastructure and support scale-out, distributed applications. Intel's Diane Bryant and Tom Krazit discussed the plans at the Gigaom Structure’14 conference in San Francisco.

In the past year, Intel has already delivered 15 custom silicon devices to meet specific needs of the end customers, including Ebay and Facebook.  The company expects to deliver more than twice the number of specialized products in 2014.

In a blog post, Bryant writes that the new Xeon+FPGA solution "provides yet another customized option, one more tool for customers to use to improve their critical data center metric of Performance/TCO”. She also highlights work underway with Facebook on the Open Compute Project and ETSI's NFV ISG to develop many proof-of-concept demonstrations.

https://communities.intel.com/community/itpeernetwork/datastack/blog/2014/06/18/disrupting-the-data-center-to-create-the-digital-services-economy

In February, Intel introduced its new Xeon processor E7 v2 family featuring triple the memory capacity and double the compute performance of the previous generation processor family, allowing much faster and thorough data analysis.

The Intel Xeon processor E7 v2 family is built for up to 32-socket servers, with configurations supporting up to 15 processing cores and up to 1.5 terabytes (TB) of memory per socket. 

To reduce data bottlenecks, the Intel Xeon Processor E7 v2 family features Intel Integrated I/O, Intel Data Direct I/O and support for PCIe 3.0, achieving up to four times the I/O bandwidth over the previous generation and providing extra capacity for storage and networking connections.

Intel said Big Data analysis and Internet-of-Everything require vastly increased in-memory processing, which places and analyzes an entire data set – such as an organization's entire customer database – in the system memory rather than on traditional disk drives.

Monday, June 16, 2014

Altera Collaborates with Microsoft on Software Defined Data Centers

Microsoft Research is testing Altera's FPGAs to accelerate its Bing search engine and other cloud services.

Details on the project were disclosed in a research paper titled, “A Reconfigurable Fabric for Accelerating Large-Scale Data Center Services” that was presented by Microsoft at the 41st International Symposium on Computer Architecture (ISCA) in Minneapolis. (link to the paper is below)

Altera’s software defined data center technology offerings are based on the company’s high performance Stratix V and Arria 10 FPGAs, and next-generation Stratix 10 FPGAs and SoCs which are manufactured using the Intel 14 nm Tri-Gate process and feature Altera’s high-performance HyperFlex architecture.

The Microsoft paper describes a testbed of 1,632 servers accelerated by FPGAs and achieving a very significant reduction in latency compared with commodity servers.

“Altera FPGAs help Microsoft meet the challenging workload requirements of high performance computing, while they help data centers stay within necessary cost, power efficiency and space limits,” said Michael Strickland, director of the Compute and Storage business unit, Altera. “Adding fine-grained FPGA acceleration to the compute fabric advances data center capabilities beyond what commodity server designs can provide.”

http://newsroom.altera.com/press-releases/altera-microsoft-datacenter.htm
http://research.microsoft.com/pubs/212001/Catapult_ISCA_2014.pdf


  • In March 2014, Altera and Intel announced their collaboration on the development of multi-die devices that leverage Intel’s package and assembly capabilities and Altera’s programmable logic technology. The collaboration is an extension of the foundry relationship between Altera and Intel, in which Intel is manufacturing Altera’s Stratix 10 FPGAs and SoCs using the 14 nm Tri-Gate process.  The new collaboration targets multi-die devices that integrates monolithic 14 nm Stratix 10 FPGAs and SoCs with other advanced components, which may include DRAM, SRAM, ASICs, processors and analog components, in a single package. 

Monday, April 8, 2013

Altera Demos 20 nm Transceiver at 32 Gbps

Altera is demonstrating the industry's first 20nm programmable device with 32-Gbps transceiver capabilities. The device is based on TSMC's 20SoC process technology.

Altera said its demo validates the performance capabilities of 20 nm silicon.

The transceiver technology will be integrated into Altera's 20 nm FPGA products, fabricated on TSMC's 20SoC process. These devices enable customers to design next-generation serial links with the lowest power consumption, fastest timing closure and the highest quality signal integrity.

Altera is currently shipping 28 nm FPGAs with monolithically integrated low-power transceivers operating at 28 Gbps.

http://www.altera.com/32gbps-20nm


See also