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Guest Column
HyperTransport
Gains Momentum in Fixing Performance Bottlenecks of Legacy
System Buses
(continued)
Each 8-bit HyperTransport link
has its own clock and control signals to differentiate
commands from address/data. This reduces clock skew and
ensures a low bit error rate over a wide range of adjacent
ElectroMagnetic Interference (EMI) conditions. HyperTransport
also supports a dynamic clock, making it possible for the host
to change the data transfer clock rate between any two
peripheral devices. This dynamic power management is very
critical in battery-powered systems. For example,
HyperTransport devices that are used in power-sensitive
systems, such as PDAs, can use HyperTransport’s stop pin to
put the HyperTransport channel in a low-power state where
virtually no power is used by the link.
HyperTransport uses Low Voltage
Differential Signaling (LVDS) technology, with a dynamically
updated differential impedance calibrator. Using LVDS
differential signaling enables the HyperTransport link to
operate at higher frequencies than previous generation buses
while delivering equivalent or better bandwidth with a fewer
number of pins. In addition, differential signaling provides a
return current path for each signal, which greatly reduces the
number of power and ground pins required by the interface.
HyperTransport links can be between 24 and 30 inches (0.6 to
0.75 meters) in length.
HyperTransport Maintains
Important Compatibility with Heavily Installed PCI
Infrastructure
One of HyperTransport’s most
important features is its complete compatibility with PCI.
This compatibility makes it easier for designers to
deploy HyperTransport. Designers can still leverage their
existing PCI infrastructure while taking advantage of the
increased bandwidth. HyperTransport
maintains register compatibility with PCI and uses the same
common programming model as PCI, thus using existing and
unchanged PCI device drivers. To allow PCI and HyperTransport devices to fully
interoperate, HyperTransport technology includes support for
PCI bus bridging semantics, PCI producer/consumer ordering for
requests, support of all three PCI address spaces
(configuration, I/O, and memory) and PCI-compatible device and
bridge headers. In addition to attributes defined for
correct operation, additional features are also specified to
maximize performance of the overall system, such as read
prefetch support and bandwidth allocation.
There’s
Scalability in HyperTransport
In
a HyperTransport link the differential data is double clocked
using Dual Data Rate (DDR). This results in an actual transfer
rate between 400 Mbps to 2 Gbps per bit and in each direction.
The total transfer rate is then between 800 Mbps for a 2-bit
wide link to 64 Gbps for a 32-bit wide link in each direction
(transmit and receive). For example, the total data transfer
rate for a 16-bit wide link running at 600 MHz in both
transmit and receive directions is 38.4 Gbps or 4.8 GB/sec.
This
flexibility in selecting the different signaling speed and the
link width allows the system designer to scale the
HyperTransport implementation to match a wide range of
application bandwidth requirements. Further, HyperTransport
technology supports bandwidth allocation within a chain to
make sure that downstream devices aren't starved of bandwidth.
This is accomplished using a dynamic insertion rate control
mechanism that approximates the bandwidth that a device would
see using round robin arbitration on a shared bus.
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