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Guest Column
HyperTransport
Gains Momentum in Fixing Performance Bottlenecks of Legacy
System Buses
(continued)
HyperTransport
Technology Fulfills I/O Needs
HyperTransport
is a highly scalable, point-to-point differential bus that
supplements or replaces legacy address, data, and Input/Output
(I/O) interfaces while maintaining backward compatibility with
PCI. HyperTransport was developed to complement the
legacy PCI bus in Workstations and PC platforms. It has found
its way into a wide range of networking, switching, storage
and imaging systems. HyperTransport
improves the internal bandwidth of these systems by more than
10 times (compared to PCI). It also leverages the existing PCI
infrastructure including any PCI device drivers as it
maintains register compatibility with PCI.
The
technology offers several system design advantages.
It provides a high-performance link for embedded
applications, and it enables highly scalable multiprocessing
systems. With up to 12.8GB/sec transfer rates, HyperTransport
allows ICs within PCs, networking and communications devices
to communicate with each other up to 24 times faster than with
existing technologies such as a 64-bit PCI bus running at 66
MHz.
See
a large view of this chart
Figure
1 illustrates a typical system block diagram based on
HyperTransport.
This
fast connection complements externally visible bus standards
like PCI, as well as emerging technologies like InfiniBand. As
systems designers adopt new technologies to increase
bandwidth, predictions are the market for interconnect ICs
will see annual growth of more than 15%.
HyperTransport: A Scalable,
Flexible Architecture
One of the key advantages of
HyperTransport is the scalability of the technology in both
channel width and data transfer rate. A HyperTransport link
can be 2, 4, 8, 16, or 32 bits wide and consist of a transmit
and a receive link. The width of a transmit or receive link
can be totally independent to suit an application’s needs.
For example, the transmit link can be 4-bits wide while the
receive link can be 16-bits wide to support different upstream
and downstream bandwidths. Similarly, the clock rate on the
link can be selected from 200MHz to 1 GHz (in 100 MHz
increment). The clock rate of the transmit and receive links
can also be independently set to meet system bandwidth and
transfer rate requirements. For example, a designer could
construct a HyperTransport link with a 2-bit wide physical
link upstream running at 400 MHz and an 8-bit wide link
downstream running at 600 MHz. The HyperTransport link does
not require any special I/O drivers, as the HyperTransport
protocol layer will ensure the proper flow of data throughout
the link. This variable asymmetric width and clock rate
capability gives the designer the ability to allocate
bandwidth specific to the needs of the system.
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