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Guest Column
HyperTransport
Gains Momentum in Fixing Performance Bottlenecks of Legacy
System Buses
(continued)
New I/O Technologies Promise
to Extend Bandwidth for Tomorrow’s System Requirements
What lies beyond the legacy PCI
bus for solving system bandwidth requirements? At 66 MHz and
64-bits wide, PCI has a peak bandwidth of 528 MB/s and a
sustainable bandwidth rate that is way below the peak rate.
This is also compounded by the fact that PCI is a shared bus,
forcing devices to contend for the limited available
bandwidth. Additionally, increasing the speed of the PCI bus
causes a corresponding decrease in maximum bus length and
number of slots or the number of devices that can share the
same bus. However, PCI is still well suited as a bus for low
speed interfaces and add-on cards.
New
serial buses and chip-to-chip technology and standards have
emerged over the past couple of years to address critical
points in system design performance and bandwidth bottlenecks.
These include HyperTransport (HT), PCI-X, PCI-Express
(formally known as 3GIO), RapidIO (RIO) and others.
Built
on top of the PCI model, PCI-Express is proposed as a new,
layered architecture for supporting high-speed media. While
the software model is compatible with PCI, the physical media
and interface specification is completely different.
The physical interface consists of low-voltage,
differentially driven pairs of signals, a packetized
transaction protocol and a set of software and physical
abstraction layers that insulate the physical media interface
from the higher layer software. PCI-Express based devices are
expected to be deployed in the latter half of 2003.
Similar
to PCI-Express, RapidIO has been proposed for both
chip-to-chip and board-to-board applications. It was initially
proposed in 1997 as a fixed 8-bit or 16-bit parallel I/O
scheme with little PCI compatibility, RapidIO has been
extended recently to include a serial physical layer
definition and a PCI-like configuration method. The RapidIO
parallel bus implementation supports many peer-to-peer
transactions and is useful in selected applications where PCI
compatibility is not an issue.
HyperTransport
publicly announced and introduced more than a year ago has gained substantial
momentum in the marketplace and is increasingly used today in
a variety of systems as the de facto choice for high-speed and
high-bandwidth chip-to-chip connections.
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