Innovium, a start-up based in San Jose, California, introduced its TERALYNX scalable Ethernet silicon for data centers switches.
Innovium said its TERALYNX will be the first single switching chip to break the 10 Tbps performance barrier, along with telemetry, line-rate programmability, the largest on-chip buffers and best-in-class low-latency. The chip is expected to sample in Q3 2017.
TERALYNX includes broad support for 10/25/40/50/100/200/400GbE Ethernet standards. It will deliver 128 ports of 100GbE, 64 ports of 200GbE or 32 ports of 400GbE in a single device. The TERALYNX switch family includes software compatible options at 12.8Tbps, 9.6Tbps, 6.4Tbps and 3.2Tbps performance points, each delivering compelling benefits for switch system vendors and data center operators.
- 12.8Tbps, 9.6Tbps, 6.4Tbps and 3.2Tbps single chip performance options at packet sizes of 300B or smaller
- Single flow performance of 400Gbps at 64B minimum packet size, 4x vs alternatives
- 70MB of on-chip buffer for superior network quality, fewer packet drops and substantially lower latency compared to off-chip buffering options
- Up to 128 ports of 100GbE, 64 ports of 200GbE or 32 ports of 400GbE, which enable flatter networks for lower Capex and fewer hops
- Support for cut-through with best-in-class low latency of less than 350ns
- Programmable, feature-rich INNOFLEX forwarding pipeline
- Comprehensive layer 2/3 forwarding and flexible tunneling including MPLS
- Large table resources with flexible allocation across L2, IPv4 and IPv6
- Line-rate, standards-based programmability to add new/custom features and protocols
- FLASHLIGHT telemetry and analytics to enable autonomous data center networks
- Extensive visibility and telemetry capabilities such as sFlow, FlexMirroring along with highly customizable extra-wide counters
- P4-INT in-band telemetry and extensions to dramatically simplify end to end analysis
- Advanced analytics enable optimal resource monitoring, utilization and congestion control allowing predictive capabilities and network automation
- SERDES I/Os for existing and upcoming networks
- Industry-leading, proven SerDes supports 10G and 25G NRZ, as well as 50G PAM4, to provide customers a variety of connectivity choices, ranging from widely deployed 10/25/40/50/100G Ethernet to upcoming 200/400GbE
- Up to 258 lanes of long-reach SerDes, each of which can be configured dynamically
- Integrated GHz ARM CPU core along with PCIe Gen 3 host connectivity
- ARM core enables development of differentiated real-time automation features
- High speed host connectivity and DMA enhancements enable high performance packet, table and telemetry data transfers while minimizing CPU overhead
- Two high-speed Ethernet ports for management or telemetry data
“Networking silicon solutions in the market today are generic, one-size-fits-all approaches and as a result, sub-optimal for data-centers. Innovium has used a unique, singular focus on data centers to deliver the strongest set of switch capabilities that dramatically advance the future of data centers,” said Rajiv Khemani, CEO & Co-founder of Innovium. “Equally important, we have assembled one of the strongest execution teams for rapid, high-volume deployments. We are excited to be working with leading switch system and data center customers as we execute on our mission.”
Innovium, in partnership with Inphi, also introduced a single switch chip based reference design for a platform supporting 12.8Tbps (128 X 100GbE) QSFP28 deployments. The reference design uses Innovium’s 12.8Tbps TERALYNX Ethernet switch silicon and Inphi’s 4-Level Pulse Amplitude Modulation (PAM4) chipset.
“As the pioneer of PAM based electronics for 40/50/100/200/400G, Inphi continues to enable a successful PAM4 ecosystem, leading the industry to the new world of terabit cloud optical interconnects. The 12.8Tbps reference design with Inphi’s PAM4 silicon in conjunction with Innovium’s new single switch chip is yet other major achievement in direct response to what data center operators require in the networking world,” said Siddharth Sheth, vice president of marketing, Networking Interconnect at Inphi.
In addition, Innovium announced $38.3 million in Series C funding from new lead investor, Redline Capital, new strategic investors and existing investors Greylock Partners, Walden Riverwood Ventures, Capricorn Investment Group, Qualcomm Ventures and S-Cubed Capital. This brings the company's total financing to $90 million/
Innovium also announced a board of advisors and investors consisting of networking industry luminaries: Yuval Bachar, Principal Engineer for Global Infrastructure Architecture at LinkedIn; Sachin Katti, Professor of EE & CS at Stanford University; Martin Lund, CEO of Metaswitch; Rajeev Madhavan, serial entrepreneur and General Partner of Clear Ventures; Pradeep Sindhu, Founder and Vice Chairman of Juniper Networks; Krishna Yarlagadda, President of Imagination Technologies; and Raj Yavatkar, VMware Fellow.