Monday, February 6, 2017

WD and Toshiba Produce First 512 Gigabit 64-Layer 3D NAND Chip

Western Digital Corp. announced pilot production of the first 512 Gigabit (Gb) three-bits-per-cell (X3) 64-layer 3D NAND (BICS3) chip in Yokkaichi, Japan, with mass production expected in the second half of 2017.

The company describes the first production as a significant achievement in a nearly three-decades-long legacy of flash memory innovations.

“The launch of the industry’s first 512Gb 64-layer 3D NAND chip is another important stride forward in the advancement of our 3D NAND technology, doubling the density from when we introduced the world’s first 64-layer architecture in July 2016,” said Dr. Siva Sivaram, executive vice president, memory technology, Western Digital. “This is a great addition to our rapidly broadening 3D NAND technology portfolio. It positions us well to continue addressing the increasing demand for storage due to rapid data growth across a wide range of customer retail, mobile and data center applications.”

The 512Gb 64-layer chip was developed jointly with the company’s technology and manufacturing partner Toshiba.

http://www.wdc.com

Western Digital Achieves First 64 Layer 3D NAND


Western Digital has achieved pilot production of 3D NAND technology in 64 layers. The technology, which WD is calling BiCS3, was developed jointly with Toshiba, its manufacturing partner. It will be initially deployed in 256 gigabit capacity and will be available in a range of capacities up to half a terabit on a single chip. WD expects commercial volumes of BiCS3 in the first half of calendar 2017. "The launch of the next generation 3D NAND...


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