ARM released a new CoreLink CMN-600 Coherent Mesh Network interconnect and CoreLink DMC-620 Dynamic Memory Controller technology enabling the latest ARM-based SoCs to offer unmatched data throughput and the lowest edge to cloud latency in the market.
- New architecture achieving higher frequencies (2.5 GHz and higher), 50 percent lower latency
- 5x higher throughput and more than 1TB/s of sustained bandwidth
- New Agile System Cache with intelligent cache allocation to enhance any sharing of data between processors, accelerators and interfaces
- Supporting CCIX the open industry standard for coherent multi-chip processor and accelerator connectivity
- CoreLink DMC-620 includes integrated ARM TrustZone security and supports 1 to 8 channels of DDR4-3200 memory and 3D stacked DRAM for up to 1TB per channel
- Accelerated SoC development and system deployment
The company said its new on-chip interconnect technology has applicability across multiple markets including 5G networks, data center infrastructure, HPC, automotive and industrial systems.
"The demands of cloud-based business models require service providers to pack more efficient computational capability into their infrastructure," said Monika Biddulph, general manager, systems and software group, ARM. "Our new CoreLink system IP for SoCs, based on the ARMv8-A architecture, delivers the flexibility to seamlessly integrate heterogeneous computing and acceleration to achieve the best balance of compute density and workload optimization within fixed power and space constraints."