Tuesday, November 19, 2013

Intel Tunes its Xeon Phi for Programming Simplicity and Performance

Intel confirmed that its next generation Xeon Phi devices (codenamed "Knights Landing"), available as a host processor, will fit into standard rack architectures and run applications entirely natively instead of requiring data to be offloaded to the coprocessor.

Intel said this approach will significantly reduce programming complexity and eliminate “offloading” of the data, thus improving performance and decreasing latencies caused by memory, PCIe and networking. Knights Landing will also offer developers three memory options to optimize performance.

In addition, Intel and Fujitsu recently announced an initiative that could potentially replace a computer’s electrical wiring with fiber optic links to carry Ethernet or PCI Express traffic over an Intel Silicon Photonics link. This enables Intel Xeon Phi coprocessors to be installed in an expansion box, separated from host Intel Xeon processors, but function as if they were still located on the motherboard. This allows for much higher density of installed coprocessors and scaling the computer capacity without affecting host server operations.

http://www.intel.com

  • In June, Intel announced five new Xeon Phi coprocessors:  the Intel Xeon Phi coprocessor 7100 family is designed and optimized to provide the best performance and offer the highest level of features, including 61 cores clocked at 1.23GHz, 16 GB of memory capacity support (double the amount previously available in accelerators or coprocessors) and over 1.2 TFlops of double precision performance. The Intel Xeon Phi coprocessor 3100 family is designed for high performance per dollar value. The family features 57 cores clocked at 1.1 GHz and 1TFlops of double precision performance. The Intel Xeon Phi coprocessor 5100 family is optimized for high-density environments with the ability to allow sockets to attach directly to a mini-board for use in blade form factors.
    Looking further ahead, the second generation Intel Xeon Phi coprocessors, codenamed "Knights Landing," will be manufactured using Intel's 14nm process technology featuring second generation 3-D tri-gate transistors.  It will be available either on a PCIe card or a host processor (CPU). As a PCIe card-based coprocessor, "Knights Landing" will handle offload workloads from the system's Intel Xeon processors and provide an upgrade path for users of current generation of coprocessors.  As a host processor directly installed in the motherboard socket, it will function as a CPU and enable the next leap in compute density and performance per watt, handling all the duties of the primary processor and the specialized coprocessor at the same time.

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