Wednesday, December 12, 2012

Vitesse and Microsemi Develop 1588v2 Sync and Timing Reference Design

Vitesse Semiconductor and Microsemi Corp. introduced a reference design for implementing IEEE 1588v2 synchronization and timing in packet-based networks.

The reference design uses Vitesse's Serval VSC7418 Carrier Ethernet Switch Engine with VeriTime 1588 technology and Microsemi's ZL30343 SyncE/IEEE1588 packet synchronizer (DPLL) and clock recovery algorithm. The reference design meets the performance demands for timing synchronization in accordance with ITU-T Recommendation G.8262/G.8261 for wireless base stations, radio network controllers, gateways, aggregation and transmission equipment, and routers while reducing design complexity.

"Our jointly developed reference design allows broadband service providers to simplify the implementation of 1588 synchronization and timing technology and streamline the transition to IP Edge networks," said Maamoun Seido, vice president for timing products at Microsemi. "Demand for precise timing and synchronization solutions is growing and we will continue to collaborate with industry leaders such as Vitesse to deliver industry-standard 1588 solutions to meet this need."

"This reference design provides our customers with a proven path to add precision timing needed for carrier access and backhaul networks," said Uday Mudoi, product marketing director at Vitesse. "Vitesse's VeriTime portfolio delivers nanosecond accurate time-stamping for both microwave and fiber networks, which when combined with the Microsemi DPLL and clock recovery algorithm, helps OEMs expedite upgrades to meet 4G/LTE network timing requirements."

http://www.vitesse.com/ce/1588-ref-design
http://www.microsemi.com



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