Friday, December 14, 2012

Avago Samples 100G Ethernet/OTN PHYs in 28nm CMOS

Avago Technologies has begun sampling its new Vortex Gearbox family of Physical Layer Transceiver (PHY) devices supporting Ethernet and Optical Transport Networking (OTN).


Avago’s Vortex Gearbox , which uses 28nm CMOS SerDes technology, also incorporates the company's proprietary Decision Feedback Equalization (DFE) architecture for low overall power consumption, low data latency and improved jitter and crosstalk performance. 
The Vortex Gearbox AVSP-1104 is a single-chip PHY IC designed for high-density 100G Ethernet and OTN applications. The device is ideal for driving both backplane and portside applications. Key features include:
  • Long reach performance withstanding up to 32dB of channel loss
  • Hole-free operation from 1-28 Gbps
  • Gearbox functionality for full-duplex conversion of four lanes (4x25 Gbps, 4x28 Gbps) to ten lanes (10x10 Gbps, 10x11 Gbps)
  • Option for configuration as a retimer function for full-duplex transmission of ten lanes
  • Programmable Tx/Rx equalization of all SerDes interfaces
  • Bit Error Rate (BER) of 1e-20

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