Tuesday, September 6, 2011

NetLogic's 28nm XLP Packs up to 80 Cores, Scales to 640 Core System

NetLogic Microsystems unveiled its next generation of XLP II family of processors based on 28nm process technology, packing up to 80 high-performance NXCPUs per chip, and promising 5-7x performance enhancement over the existing XLP processors. Target applications for the new multi-core devices include next-generation LTE mobile infrastructure, data center, enterprise networking, storage and security platforms.


NetLogic said its XLP II processor family is designed to deliver over 100 Gbps of network processing performance per device and over 800 Gbps in a clustered, fully-coherent system. The devices integrate up to 80 high-performance NXCPUs per chip, featuring an enhanced quad-issue, quad-threaded, superscalar out-of-order processor architecture capable of operating at up to 2.5 GHz to provide unmatched control and data plane processing and low-power profile.


NetLogic is adding innovations that improve pre-fetch performance, branch mis-predict penalties and cache access latencies. The family also significantly expands the tri-level cache architecture to over 32MB of fully coherent on-chip cache which represents over 260MB of on-chip cache in the maximum clustered configuration of 8 fully-coherent XLP II processors.


NetLogic is also introducing a second-generation high-speed Inter-chip Coherency Interface (ICI) that will enable systems designs with eight sockets of XLP II processors for scalability of up to 640 NXCPUs. Full processor and memory coherency are enabled across all 640 NXCPUs, allowing software applications to run in Symmetric Multi Processing (SMP) or Asymmetric Multi Processing (AMP) modes.


For the high-end of the XLP II family, to complement the 80 NXCPUs per chip, the XLP II multi-core processors include fully-autonomous hardware processing engines to accelerate a variety of networking, security and storage functions, such as:



  • CPU Virtualization Engines supporting full-virtualization and para-virtualization modes

  • Network Acceleration Engines for ingress/egress packet parsing and management

  • Packet Ordering Engines

  • Deep Packet Inspection Engines for Layer 7 application processing, intrusion prevention, malware detection and regular expression search acceleration

  • Security Acceleration Engines for encryption, decryption and authentication protocols

  • Compression/Decompression Engines

  • TCP Segmentation Offload Engines

  • RAID-5/RAID-6 Acceleration Engines

  • Storage De-Duplication Acceleration Engines

  • IEEE 1588 Hardware Time Stamping


"Building upon the performance leadership and strong design win momentum of our industry-leading XLP processor family, we are pleased to announce our revolutionary XLP II processor family featuring numerous innovations that put us a full generation ahead of competing communications multi-core solutions. We believe our highly differentiated XLP II processor is a true game-changer that will give us a significant competitive advantage in the communications infrastructure market," said Ron Jankov, president and chief executive officer at NetLogic Microsystems. "The XLP II multi-core processor family is the result of our intensive R&D development in the advanced 28nm process over the past 24 months, and our uniquely close partnership with TSMC. I congratulate our team for once again out-executing and out-innovating the communications processing industry to further extend our performance leadership and separate ourselves from the competition." http://www.netlogicmicro.com

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