Saturday, February 20, 2010

TI Unveils Multicore Architecture for Communications Equipment

Texas Instruments unveiled a new System-on-a-Chip (SoC) architecture based on its multicore digital signal processors (DSPs) and designed for the next generation of wireless base stations, media gateways and video infrastructure equipment.



Significantly, TI has integrated fixed and floating point capabilities, pushing beyond the traditional functionality of DSPs to take on the multilayer processing roles of network processors. This paves the way for highly integrated base station designs with the ability to support various access types and while retaining a low-power consumption profile.


In terms of raw performance, TI's new multicore SoCs will run at up to 1.2GHz, providing an engine with up to 256 GMACS and 128 GFLOPS -- this is over five times the performance of existing solutions in the market. The higher performance is needed to drive advanced functionality such as handling advanced matrix processing for MIMO implementations and other spectral efficiency processing.


Key features and benefits:

  • Multiple high-performance DSPs operating at up to 1.2GHz in an innovative SoC architecture;


  • Integrated fixed and floating point processing within each DSP core combining ease of use with unprecedented signal processing performance;


  • Robust suite of tools, application-specific software libraries and platform software enabling faster development cycles and more effective debug and analysis;


  • Five times the DMA capability and twice the memory per core of other SoCs ensuring robust application performance for customers;


  • Product family to include range of devices starting with four-core device for wireless base stations and eight-core device for media gateway and networking applications;


  • Direct communication between cores and memory access with TI's Multicore Navigator freeing peripheral access and unleashing multicore performance;


  • A 2 terabit per second on-chip switch fabric, TeraNet 2, providing high bandwidth and low latency interconnection of all of the SoC elements;


  • A Multicore Shared Memory Controller allowing faster on-chip and external memory access;


  • High-performance layer 1, layer 2 and network co-processors.


TI expects its products from the new multicore portfolio to begin sampling in the second half of 2010.


"Manufacturers of communications infrastructure equipment have very specific requirements for differentiating their products and innovating beyond a single portfolio. It was clear to us that TI had the opportunity to introduce a new platform to customers with a ‘smart design' approach that meets their needs for years to come," said Brian Glinsman, general manager of TI's communications infrastructure business."With this new multicore architecture, we challenged ourselves to exceed Moore's Law by bucking the trend of simply linearly increasing the amount of cores on each platform; instead, we increased overall performance with significant enhancements to the DSP, a new breed of coprocessors, and reduced power consumption."http://www.ti.com/ciplatform-pr-home

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